• 邏輯綜合和物理綜合的區別
• RC提供三種物理綜合方法
  • The simple PLE flow
  • The RC-Spatial flow
  • The RC-Physical flow
  • 物理綜合的相關文件
  • 物理綜合的層次信息
• simple PLE flow
  • read lef
  • read capacitance或者read QRC
  • 檢查或者report PLE信息
  • 合理設置綜合模式interconnect_mode屬性
  • write_design -encounter
  • Simple PLE Flow的簡單腳本
• WLM的進一步理解

綜合工具，一般有RC和DC；分別來自cadence和synopsys。
綜合，又分為邏輯綜合（logic synthesis）和物理綜合（physical synthesis）；以前只了解邏輯綜合，工藝變為28nm后，應該要額外關注物理綜合。

參考文檔：
RC用戶文檔里的rc_phys.pdf

邏輯綜合和物理綜合的區別？

邏輯綜合用的線負載模型，叫WLM；是基于pin的fanout建立的。工藝更高級，線延遲占比會越大，比如28nm，就不再適合簡單的WLM；因此出現PLE。
物理綜合不再簡單使用線負載模型，而是使用更準確的物理信息（包括位置），即與布局布線后的線延遲，在RC里叫PLE（Physical Layout Estimation），在DC里叫DC Ultra Topographical。
物理綜合與后端的協作性會更貼近，防止出現過度悲觀或者過度樂觀的設計。

RC提供三種物理綜合方法

The simple PLE flow

這個是常用的方法。
利用標準單元和memory庫的lef文件，或者PDK里的電容查找表；去得到寄生參數的電阻電容值。然后估算出線長即線延遲。
其中
LEF— The LEF libraries are the physical libraries that contain information such as layer,
via, placement site type, routing design rules, process information, and standard cell and
macro cell definitions.

Capacitance Table— Capacitance tables contain the same type of parasitic
information as the LEF files but the resistance and capacitance information in the
capacitance table is more detailed and therefore more accurate than in the LEF file. The
values in a capacitance table comes from the same process definition files that drive sign
off extraction as well as the various other extractors used in Cadence tools.

原文： uses technology information and cell areas from the LEF libraries instead of from the synthesis technology libraries. The PLE flow uses parasitic resistance and capacitance values from the LEF libraries or the capacitance tables (if available) when estimating the wire lengths.This flow works in all base RTL Compiler products.

The RC-Spatial flow

好像是指def，即前端根據IP部件劃分的面積矩形框，去安排簡單的布局。這樣與后端布局布線的線延遲參數更切合。
DEF— DEF files are ASCII files that contain information that represent the design at any
point during the layout process. In RTL Compiler, the DEF is primarily used for floorplan
information.

原文： uses in addition a rapid placement to better estimate long wires in your design. This helps deliver more accuracy to the core synthesis optimization engine during RTL-to-gate synthesis. This flow works in all base RTL Compiler products, but requires access to the Encounter Digital Implementation System.

The RC-Physical flow

這需要后端提供更精確的物理布局布線信息。

原文： uses in addition a complete placement and considers congestion and legal placement as a cost function during the RTL-to-gates phase, to create a better netlist. This flow requires an RTL Compiler Advanced Physical Option license inaddition to a base RTL Compiler product license and requires access to the Encounter Digital Implementation System.

物理綜合的相關文件

物理綜合的層次信息

simple PLE flow

read lef

In the simple PLE flow, the cellarea defined in the LEF libraries is used instead of the cell
area defined in the timing library (.lib).
The timing library area will be used if
■ The physical libraries do not contain any cell definitions.
■ You onlyread in the technology LEF file (containing only the metal routing layer information without the standard cell/macro definitions).
For best results, always use all available LEF files (standard cell, macro and technology LEF).

相關RC命令

rc:/> set_attribute lef_library {tech.lef cell.lef} ## 注意： 如果分成兩句命令定義lef_library，會發生replace的錯誤。 rc:/> get_attribute lef_library tech.lef cell.lef

rc會對lib和lef，針對它們的cell做一致性檢查，不一致會report warning。

RTL Compiler will check whether the following definitions are in the LEF file:
■ CAPACITANCE CPERSQ
■ EDGECAPACITANCE
■ RESISTANCE RPERSQ
■ SITE
■ WIDTH

read capacitance或者read QRC

Note:

• If you specify both a capacitance table file and a QRC technology file, the QRC technology file takes precedence.
• It is recommended to specify both LEF and parasitic files. However, you can specify the LEF files only, if the parasiticfiles are not available.
• Scaling factors are used to align a design with a particular process. A capacitance table is process specific where as a scaling factor is design specific. The scaling factors are provided to be consistent with Encounter. Only use a scaling factor if itwill also be used in the back-end.
• For best results, the corner for the parasitic file used should match the corner for the timing library. That is typically max or worst.

The process definition files define layer thicknesses, compositions, and spacings.

For technologies below 28nm, the Encounter Digital Implementation System requires a QRC technology file instead of a capacitance table file.

rc相關命令：

rc:/> set_attribute cap_table_file my.cap rc:/> set_attribute qrc_tec_file techfile.qrc

RTL Compiler will check if the following information is available inthe parasitic file:
■ PROCESS_VARIATION
■ BASIC_CAP_TABLE
■ width
■ Cc
■ Carea
■ Cfrg

檢查或者report PLE信息

rc:/> report ple ============================================================ Generated by: Encounter(R) RTL Compiler 10.1.100 Generated on: Apr 30 2010 03:29:32 pm Module: DTMF_CHIP Technology libraries: tsmc18 1.0 tpz973g 230 pllclk 4.3 ram_128x16A 1.1 ram_256x16A 1.1 rom_512x16A 1.1 physical_cells Operating conditions: slow Interconnect mode: global Area mode: physical library ============================================================ Aspect ratio : 1.00 Shrink factor : 1.00 Scale of res/length : 1.00 Scale of cap/length : 1.00 Net derating factor : 1.00 Site size : 5.70 um (from lef [tech+cell]) Capacitance Layer / Length Data source: Name Direction Utilization (pF/micron) cap_table_file ------------------------------------------------M1 H 1.00 0.000274 M2 V 1.00 0.000242 M3 H 1.00 0.000242 M4 V 1.00 0.000242 M5 H 1.00 0.000242 M6 V 1.00 0.000304 Resistance Layer / Length Data source: Name Direction Utilization (ohm/micron) lef_library -------------------------------------------------Metal1 H 1.00 0.439130 Metal2 V 1.00 0.360714 Metal3 H 1.00 0.360714 Metal4 V 1.00 0.360714 Metal5 H 1.00 0.360714 Metal6 V 1.00 0.102273 Area Layer / Length Data source: Name Direction Utilization (micron) lef_library -------------------------------------------------Metal1 H 1.00 0.230000 Metal2 V 1.00 0.280000 Metal3 H 1.00 0.280000 Metal4 V 1.00 0.280000 Metal5 H 1.00 0.280000 Metal6 V 1.00 0.440000 rc:/>

合理設置綜合模式–interconnect_mode屬性

默認interconnect_mode為wire load model；

如果綜合flow，吃了lef文件，interconnect_mode會默認改為PLE；

如果吃了lef文件，又想強制改為wire load model。則設置interconnect_mode為wireload；

綜上所述，物理綜合的話，要檢查interconnect_mode的設置；確認應該是PLE。

write_design -encounter

The final part of the physical flow involves exporting the data for place and route processing.
This is done through the write_design -encounter command.
The write_design -encountercommand generates the following files:
■ Netlist (.v)
■ Encounter configuration file (.conf),
■ SDC constraints (.sdc)
■ Tcl script (.enc_setup.tcl)
■ Mode file (.mode)
■ DEF file (.def)
■ Timing derate file (.derate.tcl) — generated when RTL Compiler changed the default timing derate values

Simple PLE Flow的簡單腳本

set_attribute source_verbose true / set_attribute information_level 9 / suppress_message "xxx" set_attribute enc_temp_dir rc_enc / set_attribute lib_search_path path / set_attribute library "library_list" / set_attribute lef_library "lef_list"/ set_attribute cap_table_file file/ read_hdl DESIGN/dtmf_chip.v elaborate DTMF_CHIP report ple read_sdc dtmf.sdc read_def DESIGN/floorplan/dtmf.def synthesize -to_mapped report area report qor write_design -encounter

WLM的進一步理解

參考文檔：
STA（Cadence）——Net delay_長河_新浪博客
http://blog.sina.com.cn/s/blog_436c4cf10101jf1d.html

原文如下：

目標：使用wire-load models來計算net delays，識別用于backannotation的文件格式Interconnect提供一個具有內部delay的pin to pin 的timing arc，這個delay是由于線的電阻和電容引起的，也稱之為wire delay或者net delay。另外，所有的interconnect arcs都是positively unate。net delay通常是從輸入的50%到輸出的50%。wire-delay estimation methods: (1)Physical layout estimation (PLE): 使用實際的設計和物理庫信息，動態計算不同邏輯結構下的線延遲，與布局布線強相關。輸入：lef library，capacitance table和floorplan (2)Wire-load models:wire loads的計算是寄寓最近的calibrated area，選擇一個合適的線負載模型是很費力的事情，是一個靜態的模型。輸入：wire-load models使用線負載模型(WLM)：net delay = RC (R: net resistance, C: net capcitance)，綜合工具根據90%的線的length和fanout，估算出R和C（Poisson distribution）。Wire loads提供以下信息：幾個block sizes和每個的平均capacitance，給丁一個fanout的平均net length（使用Poisson distribution），基于block的面積和net的fanout，計算電容（平均電容乘以net length）。總而言之，STA工具使用靜態的WLMs根據長度，fanout和面積來計算net的capacitance。（對于同樣的fanout，block的面積越大，估計的平均net length就越長，電容就越大）。STA工具使用基于面積的wire load選擇表來選擇合適的線負載模型。Backannotation:布局布線之后，收集extracted parasitic（RC）信息，并導入綜合工具（或者直接導入，作為parasitics；或者由delay calculator計算出delay，再導入）。這個過程就是backannotation。Backannotated information is available in the following file formats: (1) SPEF (standard parasitic exchange format): for extracted parasitics (2) DSPF (detailed standard parasitic format): for detailed extracted RC (3) RSPF (reduced standard parasitic format): for less accurate extracted parasitics (4) SDF (standard delay format): for delay informationExtraction: 布局布線之后計算RC，工具： Cadence QRC，Star RC （Synopsys） Delay Calculation： 根據RC，準確獲取物理net和cell的delays (SDF)，工具：SignalStorm nanometer delay calculator和CeltIC nanometer delay calculator (Cadence).

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