CPUFPGA混合架構(gòu)上的硬件線程加速方法-浙江大學(xué)計(jì)算機(jī)學(xué)院.PDF

ISSN 1000-9825, CODEN RUXUEW E-mail: jos@

Journal of Software , Vol.20, Supplement, December 2009, pp.15?22

? by Institute of Software , the Chinese Academy of Sciences . All rights reserved. Tel/Fax: +86-10

?

CPU/FPGA混合架構(gòu)上的硬件線程加速方法

+

陳天洲 , 嚴(yán)力科, 胡 威, 馬吉軍

(浙江大學(xué) 計(jì)算機(jī)科學(xué)與技術(shù)學(xué)院,浙江 杭州 310027)

Hardware Thread Accelerating Method Based on CPU/FPGA Hybrid Architecture

+

CHEN Tian-Zhou , YAN Li-Ke, HU Wei, MA Ji-Jun

(College of Computer Science, Zhejiang University, Hangzhou 310027, China)

+ Corresponding author: E-mail: tzchen@

Chen TZ, Yan LK, Hu W, Ma JJ. Hardware thread accelerating method based on CPU/FPGA hybrid

architecture. Journal of Software, 2009,20(Suppl.):15?22. /1000-9825/09003.htm

Abstract : The CPU/FPGA hybrid architecture is a popular reconfigurable computing architecture. In order to ease

the use of FPGA, a hardware thread approach is proposed, and a hardware thread executing mechanism is designed

to make use of the reconfigurable resources. Software thread and hardware thread can be executed in parallel while

computation-intensive tasks are assigned to hardware threads and control-intensive tasks are assigned to software

threads. Simics simulator is adopted to simulate a hybrid architecture platform, on which software and hardware

multithreading DES, MD5SUM and MergeSort algorithms are evaluated. The results show that the average speedup

is 2.30, and it proves that the approach explored the performance of CPU/FPGA hybrid architecture efficiently.

Key words : hardware acceleration; hardware thread; multithreading; CPU/FPGA hybrid architecture;

reconfigurable computing

摘 要: CPU/FPGA 混合架構(gòu)是可重構(gòu)計(jì)算的普遍結(jié)構(gòu),為了簡(jiǎn)化混合架構(gòu)上FPGA 的使用,提

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