錯誤信息如下：

[DRC NSTD-1] Unspecified I/O Standard: 102 out of 102 logical ports use I/O standard (IOSTANDARD) value ‘DEFAULT’, instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: dout_ch1[23:0], dout_ch2[23:0], dout_ch3[23:0], dout_ch4[23:0], clk, dout_valid_ch1, dout_valid_ch2, dout_valid_ch3, dout_valid_ch4, and rstn.

[DRC UCIO-1] Unconstrained Logical Port: 102 out of 102 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: dout_ch1[23:0], dout_ch2[23:0], dout_ch3[23:0], dout_ch4[23:0], clk, dout_valid_ch1, dout_valid_ch2, dout_valid_ch3, dout_valid_ch4, and rstn.

剛開始很奇怪，因為這些報錯的信號在bd中是中間信號（如下圖），我也沒有給它們創建port，這些vivado卻要給它們分配引腳，打開IO ports窗口，發現它們都被隨機分配了引腳，這是怎么回事呢？

百度發現，有很多人遇到了這個問題，解決方法也記錄在Xilinx官網中：

Vivado write_bitstream - ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - X out of Y logical ports use I/O standard (IOSTANDARD) value ‘DEFAULT’, instead of a user assigned specific value

解決方案是對vivado進行設置，讓其忽略這些未在約束中分配引腳的信號。這樣設置之后可以生成比特流了。

但是這個錯誤是怎么產生的呢？經過幾個小時的折騰，我發現Source中的Top不知道什么時候被改變了，應該是wrapper才對啊，原來是將一個中間文件設為了Top，那當然vivado要給它的端口信號分配引腳了，原來如此！

Top改為wrapper后，生成比特流就不出錯了！

記錄一下，小問題查起來也很花時間。

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