32.210内存的知识
32.210內存的知識
210可尋址的空間是4GB大小，內存的起始地址是20000000，前面知道2440使用的內存是SDRAM，6410使用的內存是DDR，這里210使用的是DDR2.在210的地址空間中零地址處跟6410一樣也是映射鏡像區，例如當選擇從NandFlash啟動的使用，就會把IROM的空間映射到0地址處。
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內存芯片連接：
在2440和6410兩款芯片中，它們的數據寬度是16bits，為了得到32bits的數據寬度，采用的是兩片芯片級聯的方式。而210采用的數據寬度是8bits的，要擴張成32bits，所以需要4片級聯。每一片的大小是128MB，有四片總大小512MB。有一些芯片是8片的，構成1GB*32的內存芯片。
芯片手冊里DMC0對應的是上圖中的DRAM0，DMC1對應DRAM1.
接下來就是初始化DRAM0這512MB內存。
初始化流程：
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Initialization sequence for DDR2 memory type:
1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.
2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_on bit-field to '1' to turn on the PHY DLL.
3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value according to clock frequency and memory tAC parameters.
4. Set the PhyControl0.ctrl_start bit-field to '1'.
5. Set the ConControl. At this moment, an auto refresh counter should be off.
6. Set the MemControl. At this moment, all power down modes should be off.
7. Set the MemConfig0 register. If there are two external memory chips, set the MemConfig1 register.
8. Set the PrechConfig and PwrdnConfig registers.
9. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC parameters.
10. If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers.
11. Wait for the PhyStatus0.ctrl_locked bit-fields to change to '1'. Check whether PHY DLL is locked.
12. PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT) variation during memory operation. Therefore, PHY DLL should not be off for reliable operation. It can be off except runs at low frequency. If off mode is used, set the PhyControl0.ctrl_force bit-field to correct value according to the PhyStatus0.ctrl_lock_value[9:2] bit-field to fix delay amount. Clear the PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL.
13. Confirm whether stable clock is issued minimum 200us after power on
14. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level.
15. Wait for minimum 400ns.
16. Issue a PALL command using the DirectCmd register.
17. Issue an EMRS2 command using the DirectCmd register to program the operating parameters.
18. Issue an EMRS3 command using the DirectCmd register to program the operating parameters.
19. Issue an EMRS command using the DirectCmd register to enable the memory DLLs.
20. Issue a MRS command using the DirectCmd register to reset the memory DLL.
21. Issue a PALL command using the DirectCmd register.
22. Issue two Auto Refresh commands using the DirectCmd register.
23. Issue a MRS command using the DirectCmd register to program the operating parameters without resetting the memory DLL.
24. Wait for minimum 200 clock cycles.
25. Issue an EMRS command using the DirectCmd register to program the operating parameters. If OCD calibration is not used, issue an EMRS command to set OCD Calibration Default. After that, issue an EMRS command to exit OCD Calibration Mode and to program the operating parameters.
26. If there are two external memory chips, perform steps 14~25 for chip1 memory device.
27. Set the ConControl to turn on an auto refresh counter. 28. If power down modes is required, set the MemControl registers.
先建立框架：
4.是在start.S里加入內存初始化的標識：
5.編譯一下，看看是否出錯：
沒有報錯說明框架沒問題，接下來就是mem.S的初始化代碼。
1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.
這是電源為控制器和內存設備提供穩定電壓的要求，是硬件的，略過。
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2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_on bit-field to '1' to turn on the PHY DLL.
這里是要設置PhyControl0寄存器的ctrl_start_point位和ctrl_inc位，根據時鐘頻率，還有就是設置ctrl_dll_on來打開PHY DLL。
@ step 2.1
????ldr????r0, =DMC_PHYCONTROL0
????ldr????r1, =0x00101000????????????????
????str????r1, [r0]
????
????@ step 2.2
????ldr????r0, =DMC_PHYCONTROL0
????ldr????r1, =0x00101002????????????????????
????str????r1, [r0]
3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value according to clock frequency and memory tAC parameters.
沒有使用跳過。
4. Set the PhyControl0.ctrl_start bit-field to '1'.
????@ step 4
????ldr????r0, =DMC_PHYCONTROL0
????ldr????r1, =0x00101003????????????????????
????str????r1, [r0]
5. Set the ConControl. At this moment, an auto refresh counter should be off.
@ step 5
????ldr????r0, =DMC_CONCONTROL????????????????
????ldr????r1, =0x0FFF1350
????str????r1, [r0]
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6. Set the MemControl. At this moment, all power down modes should be off.
@ step 6
????ldr????r0, =DMC_MEMCONTROL
????ldr????r1, =DMC0_MEMCONTROL????????????????
????str????r1, [r0]
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7. Set the MemConfig0 register. If there are two external memory chips, set the MemConfig1 register.
@ step 7
????ldr????r0, =DMC_MEMCONFIG0
????ldr????r1, =DMC0_MEMCONFIG_0????????????????
????str????r1, [r0]
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8. Set the PrechConfig and PwrdnConfig registers.
@ step 8
????ldr????r0, =DMC_PRECHCONFIG
????ldr????r1, =0xFF000000????????????????????
????str????r1, [r0]
9. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC parameters.
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#define DMC_PHYCONTROL0 0xf0000018
#define DMC_PHYCONTROL1 0xf000001c
#define DMC_CONCONTROL 0xf0000000
#define DMC_MEMCONTROL 0xf0000004
#define DMC_MEMCONFIG0 0xf0000008
#define DMC_MEMCONFIG1 0xf000000c
#define DMC_PRECHCONFIG 0xf0000014
#define DMC_TIMINGAREF ????0xf0000030
#define DMC_TIMINGROW ????0xf0000034
#define DMC_TIMINGDATA ????0xf0000038
#define DMC_TIMINGPOWER 0xf000003c
#define DMC_PHYSTATUS 0xf0000040
#define DMC_DIRECTCMD ????0xf0000010
#define DMC_PWRDNCONFIG 0xf0000028
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#define DMC0_MEMCONTROL????????????0x00202400
#define DMC0_MEMCONFIG_0????????0x20F00313????
#define DMC0_MEMCONFIG_1????????0x00F00313????
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#define DMC0_TIMINGA_REF 0x00000618
#define DMC0_TIMING_ROW 0x2B34438A
#define DMC0_TIMING_DATA 0x24240000
#define DMC0_TIMING_PWR 0x0BDC0343
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.globl mem_init
mem_init:
????@ step 2.1 Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc
????ldr????r0, =DMC_PHYCONTROL0
????ldr????r1, =0x00101000????????????????
????str????r1, [r0]
????
????@ step 2.2 Set the PhyControl0.ctrl_dll_on bit-field to '1' to turn on the PHY DLL.
????ldr????r0, =DMC_PHYCONTROL0
????ldr????r1, =0x00101002????@是在上面的基礎上修改????????????????
????str????r1, [r0]
????
????@ step 4
????ldr????r0, =DMC_PHYCONTROL0
????ldr????r1, =0x00101003????????????????????
????str????r1, [r0]
????
????@ step 5
????ldr????r0, =DMC_CONCONTROL????????????????
????ldr????r1, =0x0FFF1350
????str????r1, [r0]
????
????@ step 6
????ldr????r0, =DMC_MEMCONTROL
????ldr????r1, =DMC0_MEMCONTROL????????????????
????str????r1, [r0]
????
????@ step 7
????ldr????r0, =DMC_MEMCONFIG0
????ldr????r1, =DMC0_MEMCONFIG_0????????????????
????str????r1, [r0]
????
????@ step 8
????ldr????r0, =DMC_PRECHCONFIG
????ldr????r1, =0xFF000000????????????????????
????str????r1, [r0]
????
????@ step 9.1
????ldr????r0, =DMC_TIMINGAREF
????ldr????r1, =DMC0_TIMINGA_REF????????????????
????str????r1, [r0]
????
????@ step 9.2
????ldr????r0, =DMC_TIMINGROW
????ldr????r1, =DMC0_TIMING_ROW????????????????
????str????r1, [r0]
????
????@ step 9.3
????ldr????r0, =DMC_TIMINGDATA
????ldr????r1, =DMC0_TIMING_DATA????????????????
????str????r1, [r0]
????
????@ step 9.4
????ldr????r0, =DMC_TIMINGPOWER
????ldr????r1, =DMC0_TIMING_PWR????????????????
????str????r1, [r0]
????
????@ step 11
wait_lock:
????ldr????r0, =DMC_PHYSTATUS
????ldr????r1, [r0]????????????
????and????r2, r1, #0x4
????cmp????r2, #0x4????????????????????
????bne????wait_lock
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????@ step 14
????ldr????r0, =DMC_DIRECTCMD
????ldr????r1, =0x07000000????????????????????
????str????r1, [r0]
????
????@ step 16
????ldr????r1, =0x01000000????????????????????
????str????r1, [r0]
????
????@ step 17
????ldr????r1, =0x00020000????????????????????
????str????r1, [r0]
????
????@ step 18
????ldr????r1, =0x00030000????????????????????
????str????r1, [r0]
????
????@ step 19
????ldr????r1, =0x00010400????????????????????
????str????r1, [r0]
????
????@ step 20
????ldr????r1, =0x00000542????????????????????
????str????r1, [r0]
????
????@ step 21
????ldr????r1, =0x01000000????????????????????
????str????r1, [r0]
????
????@ step 22.1
????ldr????r1, =0x05000000????????????????????
????str????r1, [r0]
????
????@ step 22.2
????ldr????r1, =0x05000000????????????????????
????str????r1, [r0]
????
????@ step 23
????ldr????r1, =0x00000442????????????????????
????str????r1, [r0]
????
????@ step 25.1
????ldr????r1, =0x00010780????????????????????
????str????r1, [r0]
????
????@ step 25.2
????ldr????r1, =0x00010400????????????????????
????str????r1, [r0]
????
????@ step 26, repeat step14~step25
????ldr????r1, =0x07100000????????????????????
????str????r1, [r0]
????
????ldr????r1, =0x01100000????????????????????
????str????r1, [r0]
????
????ldr????r1, =0x00120000????????????????????
????str????r1, [r0]
????
????ldr????r1, =0x00130000????????????????????
????str????r1, [r0]
????
????ldr????r1, =0x00110400????????????????????
????str????r1, [r0]
????
????ldr????r1, =0x00100542????????????????????
????str????r1, [r0]
????
????ldr????r1, =0x01100000????????????????????
????str????r1, [r0]
????
????ldr????r1, =0x05100000????????????????????
????str????r1, [r0]
????
????ldr????r1, =0x05100000????????????????????
????str????r1, [r0]
????
????ldr????r1, =0x00100442????????????????????
????str????r1, [r0]
????
????ldr????r1, =0x00110780????????????????????
????str????r1, [r0]
????
????ldr????r1, =0x00110400????????????????????
????str????r1, [r0]
????
????@ step 27
????ldr r0, =DMC_CONCONTROL
????ldr????r1, =0x0FF02030????????????????????
????str????r1, [r0]
????
????ldr r0, =DMC_PWRDNCONFIG
????ldr????r1, =0xFFFF00FF????????????????????
????str????r1, [r0]
????
????ldr r0, =DMC_CONCONTROL
????ldr????r1, =0x00202400????????????????????
????str????r1, [r0]
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????mov????pc, lr
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轉載于:https://www.cnblogs.com/FORFISH/p/5188755.html
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