1、參考

UG585

網(wǎng)絡筆記

2、理論知識

見中斷部分

3、實驗目的

練習使用PL側的普通信號來中斷PS處理器。

4、實驗過程

建立工程，設置并初始化串口中斷，在運行程序之后，如果串口接收到N(1-63)個字節(jié)數(shù)據(jù)，則產(chǎn)生串口中斷，Zynq響應中斷，將數(shù)據(jù)從RXFIFO讀出之后寫入到DDR3預定的地址中。

5、實驗平臺

Microphase ZUS zynq7020 開發(fā)板。 串口使用 uart1[48,49]. DDR選擇 MT41J256M16 RE-125，32bit. BANK1 = 1.8v.

6、Vivado 建立工程

block design 如下：

7、SDK的工程程序

/******************************************************************************

*

* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.

*

* Permission is hereby granted, free of charge, to any person obtaining a copy

* of this software and associated documentation files (the "Software"), to deal

* in the Software without restriction, including without limitation the rights

* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

* copies of the Software, and to permit persons to whom the Software is

* furnished to do so, subject to the following conditions:

*

* The above copyright notice and this permission notice shall be included in

* all copies or substantial portions of the Software.

*

* Use of the Software is limited solely to applications:

* (a) running on a Xilinx device, or

* (b) that interact with a Xilinx device through a bus or interconnect.

*

* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,

* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF

* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE

* SOFTWARE.

*

* Except as contained in this notice, the name of the Xilinx shall not be used

* in advertising or otherwise to promote the sale, use or other dealings in

* this Software without prior written authorization from Xilinx.

*

******************************************************************************/

#include

#include "platform.h"

#include "xil_printf.h"

#include "xscugic.h"

#include "xscutimer.h"

#include "xparameters.h"

#include "xil_exception.h"

#include //sleep() usleep()

#define INTC_DEVICE_ID XPAR_PS7_SCUGIC_0_DEVICE_ID

#defineINTC_PL_INTERRUPT_ID XPAR_FABRIC_MY_AXI4LITE_IP_0_PL_TO_ZYNQ_IRQ_INTR

#defineINT_TYPE_MASK0x01

#define INT_TYPE_RISING_EDGE 0X03

#define INT_TYPE_HIGHLEVEL 0X01

#define INT_CFG0_OFFSET 0x00000C00 //(intID/16 )*4

#define INT_ENABLE_OFFSET 0x00000100 //(intID/32 )*4

#define INT_CLEAR_OFFSET 0x00000280 //(intID/32 )*4

#define INT_PRIORITY_OFFSET 0x00000400 //(intID/4 )*4

#define INT_PROCESSORTARGET_OFFSET 0x00000800 //(intID/4 )*4

#define INT_ICCPMR_OFFSET 0xF8F00104

#define INT_ICCICR_OFFSET 0xF8F00100

#define BRAM_BASS_ADDRESS 0X40000000

XScuGicINTCInst;

staticvoidPLIRQIntrHandler(void*InstancePtr); //中斷處理功能函數(shù)

static void CPU_Init(void);

static void IntcTypeSetup(XScuGic *InstancePtr, int intId, int intType) ;

static void IntcTypeEnable(XScuGic *InstancePtr, int intId, int intMask) ;

static void IntcTypeClear(XScuGic *InstancePtr, int intId ) ;

staticintInterruptSystemSetup(XScuGic* XScuGicInstancePtr); //中斷系統(tǒng)建立

static intIntcInitFunction(u16 DeviceID); //中斷控制器初始化功能

int main()

{

init_platform();

CPU_Init();

int status;

//中斷建立

status = IntcInitFunction(INTC_DEVICE_ID);

if(status != XST_SUCCESS)

returnXST_FAILURE ;

print(">>>>>>>>>>>> TEST Start >>>>>>>>>>>>>>>>\n\r");

print(" Press the Key for PL begin write data to PS DDR3 : \n\r");

while(1)

{

;

}

cleanup_platform();

return 0;

}

// 中斷控制器初始化功能

static int IntcInitFunction(u16 DeviceId)

{

XScuGic_Config* IntcConfig ;

intstatus;

printf("Enter the interrupt system >>>>>>\n");

// 第二步， 對中斷控制器進行初始化

IntcConfig = XScuGic_LookupConfig(DeviceId); //查找 GIC 的ID

status = XScuGic_CfgInitialize(&INTCInst, IntcConfig, IntcConfig->CpuBaseAddress);

if(status != XST_SUCCESS)

return XST_FAILURE;

//第三步，建立中斷系統(tǒng)

status = InterruptSystemSetup(&INTCInst);

if(status != XST_SUCCESS)

returnXST_FAILURE ;

//第四步，GPIO中斷連接到GIC上

status = XScuGic_Connect(&INTCInst, INTC_PL_INTERRUPT_ID,

(Xil_ExceptionHandler)PLIRQIntrHandler, (void *)1);

if(status != XST_SUCCESS)

returnXST_FAILURE ;

//******************//

// 參考

IntcTypeSetup(&INTCInst, INTC_PL_INTERRUPT_ID, INT_TYPE_RISING_EDGE); //重要

IntcTypeEnable(&INTCInst, INTC_PL_INTERRUPT_ID, INT_TYPE_MASK);

//*********************************//

XScuGic_Enable(&INTCInst, INTC_PL_INTERRUPT_ID); //CIG允許中斷

return XST_SUCCESS ;

}

static int InterruptSystemSetup (XScuGic * XScuGicInstancePtr)

{

//中斷異常的處理,指定該中斷異常的處理器

Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,

(Xil_ExceptionHandler)XScuGic_InterruptHandler, XScuGicInstancePtr);

Xil_ExceptionEnable(); //異常處理使能

return XST_SUCCESS;

}

void IntcTypeSetup(XScuGic *InstancePtr, int intId, int intType)

{

//Setup 包括 觸發(fā)方式配置， 優(yōu)先級配置，CPU連接。 設置某個中斷信息的前提是不影響其他中斷設置

int mask;

//設置邊沿觸發(fā)方式

mask = XScuGic_DistReadReg(InstancePtr, INT_CFG0_OFFSET + (intId/16)*4); //read ICDICFR *4,因為1個寄存器4個字節(jié)

mask &= ~(0X3 << (intId%16)*2); //把讀出的值對應2bit，清00，其他保持不變 //*2因為每個中斷對應2bit

mask |= intType << ((intId%16)*2); //把清0后的值對應2bit，寫01，其他保持不變

XScuGic_DistWriteReg(InstancePtr, INT_CFG0_OFFSET + (intId/16)*4, mask); //WRITE ICDICFR

//設置優(yōu)先級

mask = XScuGic_DistReadReg(InstancePtr, INT_PRIORITY_OFFSET + (intId/4)*4); //read 優(yōu)先級狀態(tài)

mask &= ~(0XFE << (intId%4)*8); //把讀出的值對應8bit，清00，其他保持不變 //*8因為每個中斷對應8bit

mask |= 0XA0 << ((intId%4)*8); //把清0后的值對應8bit，寫A0，其他保持不變

XScuGic_DistWriteReg(InstancePtr, INT_PRIORITY_OFFSET + (intId/4)*4, mask); //WRITE ICDICFR

//設置處理器CPIID

mask = XScuGic_DistReadReg(InstancePtr, INT_PROCESSORTARGET_OFFSET + (intId/4)*4); //read 優(yōu)先級狀態(tài)

mask &= ~(0X03 << (intId%4)*8); //把讀出的值對應8bit，清00，其他保持不變 //*8因為每個中斷對應8bit

mask |= 0X01 << ((intId%4)*8); //把清0后的值對應8bit，寫A0，其他保持不變

XScuGic_DistWriteReg(InstancePtr, INT_PROCESSORTARGET_OFFSET + (intId/4)*4, mask); //WRITE ICDICFR

}

void IntcTypeEnable(XScuGic *InstancePtr, int intId,int intMask)

{

// 本函數(shù) 只包括 使能中斷。使能之前先判斷是否需要屏蔽

int mask;

mask = XScuGic_DistReadReg(InstancePtr, INT_ENABLE_OFFSET + (intId/32)*4);

mask &= ~(0x01 << (intId%32)*1); //把對應的Enable bit 清0

mask |= intMask << ((intId%32)*1); //把對應的Enable bit 與 mask

XScuGic_DistWriteReg(InstancePtr, INT_ENABLE_OFFSET + (intId/32)*4, mask); //WRITE ICDICFR

}

void IntcTypeClear(XScuGic *InstancePtr, int intId )

{

//本函數(shù)僅包括清楚中斷，注意只能清除本中斷對應的寄存器位

int mask;

mask = XScuGic_DistReadReg(InstancePtr, INT_CLEAR_OFFSET + (intId/32)*4); //read ICDICPR

mask &= ~(0x01 << (intId%32)*1);

mask |= 0x01 << ((intId%32)*1);

XScuGic_DistWriteReg(InstancePtr, INT_CLEAR_OFFSET + (intId/32)*4, mask); //WRITE ICDICPR

}

void CPU_Init( )

{

//中斷優(yōu)先級都是A0,優(yōu)先級高于F0，CPU可接受這些中斷

Xil_Out32(INT_ICCPMR_OFFSET,0xF0);

//處理器能接收IRQ，使能中斷信號連接到處理器

Xil_Out32(INT_ICCICR_OFFSET,0x07);

}

static void PLIRQIntrHandler(void * InstancePtr)

{

//default led all turn off

printf("\n************* test STARAT *********************\n");

int i;

int readdata;

sleep(1);

for(i = 0; i < 4; i++)

{

readdata = Xil_In32(BRAM_BASS_ADDRESS+i*4); //讀取數(shù)據(jù)函數(shù)。

sleep(1);

printf("the read address is 0x%04x, the read data is 0x%04x.\n", BRAM_BASS_ADDRESS+i*4, readdata);

}

printf("\n************* test finish *********************\n");

// ***************************************************** //

IntcTypeClear(&INTCInst, INTC_PL_INTERRUPT_ID);

IntcTypeEnable(&INTCInst, INTC_PL_INTERRUPT_ID, INT_TYPE_MASK);

}

8 調(diào)試結果

總結

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