計(jì)算機(jī)指令格式

指令格式 (Instruction format )

Instruction format describes the internal structures (layout design) of the bits of an instruction, in terms of its constituent parts.

指令格式按照指令的組成部分描述指令位的內(nèi)部結(jié)構(gòu)(布局設(shè)計(jì))。

An Instruction format must include an opcode, and address is dependent on an availability of particular operands.

指令格式必須包含操作碼，并且地址取決于特定操作數(shù)的可用性。

The format can be implicit or explicit which will indicate the addressing mode for each operand.

格式可以是隱式或顯式的，這將指示每個(gè)操作數(shù)的尋址模式。

Designing of an Instruction format is very complex. As we know a computer uses a variety of instructional. There are many designing issues which affect the instructional design, some of them are given are below:

指令格式的設(shè)計(jì)非常復(fù)雜。 眾所周知，計(jì)算機(jī)使用各種指令。 有許多影響教學(xué)設(shè)計(jì)的設(shè)計(jì)問題，下面列出其中一些：

• Instruction length: It is a most basic issue of the format design. A longer will be the instruction it means more time is needed to fetch the instruction.指令長(zhǎng)度：這是格式設(shè)計(jì)的最基本問題。 指令越長(zhǎng)，則意味著需要更多的時(shí)間來(lái)提取指令。
• Memory size: If larger memory range is to be addressed then more bits will be required in the address field.存儲(chǔ)器大小：如果要尋址更大的存儲(chǔ)器范圍，則地址字段中將需要更多位。
• Memory organization: If the system supports the virtual memory then memory range which needs to be addressed by the instruction, is larger than the physical memory.內(nèi)存組織：如果系統(tǒng)支持虛擬內(nèi)存，則該指令需要解決的內(nèi)存范圍大于物理內(nèi)存。
• Memory transfer length: Instruction length should be equal to the data bus length or it should be multiple of it.內(nèi)存?zhèn)鬏旈L(zhǎng)度：指令長(zhǎng)度應(yīng)等于數(shù)據(jù)總線長(zhǎng)度，或者應(yīng)為數(shù)據(jù)總線長(zhǎng)度的倍數(shù)。

Instruction formats are classified into 5 types based on the type of the CPU organization. CPU organization is divided into three types based on the availability of the ALU operands, which are as follows here:

根據(jù)CPU組織的類型， 指令格式分為5種類型。 根據(jù)ALU操作數(shù)的可用性，CPU的組織分為三種類型，如下所示：

1) STACK CPU

1)堆棧CPU

In this organization, ALU operands are performed only on a stack data. This means that both of the ALU operations are always required in the stack. The same stack is also used as the destination. In the stack, we can perform insert and deletion operation at only one end which is called as the top of a stack. So in this format, there is no need of address because in this TOS becomes the default location.

在這種組織中，僅對(duì)堆棧數(shù)據(jù)執(zhí)行ALU操作數(shù)。 這意味著在堆棧中始終需要兩個(gè)ALU操作。 相同的堆棧也用作目標(biāo)。 在堆棧中，我們只能在稱為堆棧頂部的一端執(zhí)行插入和刪除操作。 因此，以這種格式，不需要地址，因?yàn)樵诖薚OS中，它成為默認(rèn)位置。

In this organization, only the ALU operands are zero address operation whereas data transfer instructions are not a zero address instruction. The computable instruction format of STACK CPU is Zero Address Instruction Format.

在這種組織中，只有ALU操作數(shù)是零地址操作，而數(shù)據(jù)傳輸指令不是零地址指令。 STACK CPU的可計(jì)算指令格式為零地址指令格式 。

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2) Accumulator CPU

2)累加器CPU

In this organization, one of the ALU operands is always present in the accumulator. The same accumulator is also used as the destination. Another ALU operand is present either in the register or in memory. In processor design, only one accumulator is present so it becomes the default location.

在這種組織中，累加器中始終存在一個(gè)ALU操作數(shù)。 同一累加器也用作目標(biāo)。 寄存器或存儲(chǔ)器中存在另一個(gè)ALU操作數(shù)。 在處理器設(shè)計(jì)中，僅存在一個(gè)累加器，因此它成為默認(rèn)位置。

The computable instruction format of Accumulator CPU is One Address Instruction Format.

累加器CPU的可計(jì)算指令格式為“ 一個(gè)地址指令格式” 。

3) General Register CPU

3)通用寄存器CPU

Based on the number of the registers possible in the processors, the architecture is divided into two types:

根據(jù)處理器中可能存在的寄存器數(shù)量，該體系結(jié)構(gòu)分為兩種類型：

Register-Memory references CPU

寄存器存儲(chǔ)器參考CPU

Register-Register references CPU

寄存器-寄存器引用CPU

i) Register-Memory Reference CPU

i)寄存器存儲(chǔ)器參考CPU

In this architecture, processors support less number of registers. Therefore register file size is small. In this organization, the first ALU operand is always required in the register. The same register can also be used as the destination. The second ALU operand is present either in a register or in memory. The computable instruction format of the register to memory reference CPU is Two Address Instruction Format.

在這種體系結(jié)構(gòu)中，處理器支持較少數(shù)量的寄存器。 因此，寄存器文件的大小很小。 在這種組織中，寄存器中始終需要第一個(gè)ALU操作數(shù)。 相同的寄存器也可用作目標(biāo)。 第二個(gè)ALU操作數(shù)存在于寄存器或存儲(chǔ)器中。 寄存器到存儲(chǔ)器參考CPU的可計(jì)算指令格式為“ 兩個(gè)地址指令格式” 。

ii) Register-Register Reference CPU

ii)寄存器-寄存器參考CPU

In this architecture, processors support number of registers, therefore, register file size is large. In this organization, ALU operands are performed only on a registers data that means both of the ALU operands are required in the register. Due to more number of register present in the CPU, the separate register is used to store the result. The computable instruction format of Register-Register Reference CPU is Three Address Instruction Format.

在這種體系結(jié)構(gòu)中，處理器支持寄存器的數(shù)量，因此，寄存器文件的大小很大。 在這種組織中，僅對(duì)寄存器數(shù)據(jù)執(zhí)行ALU操作數(shù)，這意味著寄存器中需要兩個(gè)ALU操作數(shù)。 由于CPU中存在更多的寄存器，因此使用單獨(dú)的寄存器存儲(chǔ)結(jié)果。 寄存器-寄存器參考CPU的可計(jì)算指令格式為三地址指令格式。

Four Address instruction format

四地址指令格式

This format contains the 4 different address fields with an opcode. Since PC is used as the mandatory register in the CPU design which is used to hold the next instruction address. So four instruction format is not in the use.

此格式包含4個(gè)不同的地址字段和一個(gè)操作碼。 由于PC被用作CPU設(shè)計(jì)中的強(qiáng)制寄存器，用于保存下一條指令地址。 因此沒有使用四種指令格式。

翻譯自: https://www.includehelp.com/cso/instruction-format.aspx

計(jì)算機(jī)指令格式

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