S32K144(18)LPI2C
1、簡(jiǎn)介
LPI2C可以用來(lái)實(shí)現(xiàn)2線(xiàn)或4線(xiàn)I2C串行總線(xiàn)。
2、信號(hào)方向
| SCL | LPI2C clock line | SCL | In 4-wire mode, this is the SCL input pin |
| SDA | LPI2C data line | SDA | In 4-wire mode, this is the SDA input pin |
| HREQ | Host request | if host request is asserted and the I2C bus is idle, then it will initiate an LPI2C ?master transfer | |
| SCLS | Secondary I2C clock line | Not Used | In 4-wire mode, this is the SCLS output pin. If LPI2C master/slave are configured to use separate pins, then this the LPI2C slave SCL pin |
| SDAS | Secondary I2C data line | Not Used | In 4-wire mode, this is the SDAS output pin. If LPI2C master/slave are configured to use separate pins, then this the LPI2C slave SDA pin |
2.1、2-wire接法
2.2、4-wire接法
3、寄存器
與SPI極度相似
3.1、Version ID Register (VERID)
版本id寄存器
3.2、Parameter Register (PARAM)
主機(jī)接收和發(fā)送FIFO大小
3.3、Master Control Register (MCR)
| 0 MEN | 主機(jī)使能 |
| 1 RST | 軟件復(fù)位 |
| 2 DOZEN | Doze模式使能 |
| 3 DEGEN | 調(diào)試模式使能 |
| 8 RTF | 復(fù)位發(fā)送FIFO |
| 9 RRF | 復(fù)位接收FIFO |
3.4、?Master Status Register (MSR)
| 0 TDF | 發(fā)送數(shù)據(jù)標(biāo)志 0:沒(méi)有請(qǐng)求發(fā)送數(shù)據(jù) 1:請(qǐng)求發(fā)送數(shù)據(jù) |
| 1 RDF | 接收數(shù)據(jù)標(biāo)志 0:沒(méi)有準(zhǔn)備好的接收數(shù)據(jù) 1:接收數(shù)據(jù)就緒 |
| 8 EPF | 結(jié)束包標(biāo)志 |
| 9 SDF | 停止檢測(cè)標(biāo)志 |
| 10 NDF | NACK檢測(cè)標(biāo)志 |
| 11 ALF | 仲裁標(biāo)志 |
| 12 FEF | FIFO錯(cuò)誤標(biāo)志 |
| 13 PLTF | 引腳低電平超時(shí)標(biāo)志 |
| 14 DMF | 數(shù)據(jù)匹配標(biāo)志 |
| 24 BBF | 主機(jī)忙標(biāo)志 |
| 25 BBF | 總線(xiàn)忙標(biāo)志 |
3.5、?Master Interrupt Enable Register (MIER)
| 0 TDIE | 發(fā)送數(shù)據(jù)中斷 |
| 1 RDIE | 接收數(shù)據(jù)中斷 |
| 8 EPIE | 結(jié)束包中斷 |
| 9 SDIE | 停止檢測(cè)中斷 |
| 10 NDIE | NACK檢測(cè)中斷 |
| 11 ALIE | 仲裁中斷 |
| 12 FEIE | FIFO錯(cuò)誤中斷 |
| 13 PLTIE | 引腳低電平超時(shí)中斷 |
| 14 DMIE | 數(shù)據(jù)匹配中斷 |
3.6、?Master DMA Enable Register (MDER)
接收數(shù)據(jù)DMA使能
3.7、Master Configuration Register 0 (MCFGR0)
| 0 HREN | 主機(jī)請(qǐng)求使能 |
| 1 HRPOL | 配置主機(jī)請(qǐng)求引腳電平 |
| 2 HRSEL | 主機(jī)請(qǐng)求選擇 |
| 8 CIRFIFO | 循環(huán)FIFO使能 |
| 9 RDMO | 只接收數(shù)據(jù)匹配 |
3.8、?Master Configuration Register 1 (MCFGR1)
?
| 0-2 PRESCALE | 分頻設(shè)置 |
| 8 AUTOSTOP | 自動(dòng)停止條件 |
| 9 IGNACK | 設(shè)置是否接收ACK、NACK |
| 10 TIMECFG | 超時(shí)操作 |
| 16-18 MATCFG | 匹配設(shè)置 |
| 24-26 PINCFG | 引腳設(shè)置 |
?3.9、Master Configuration Register 2 (MCFGR2)
| 0-11 BUSIDLE | 總線(xiàn)idle超時(shí) |
| 16-19 FILTSCL | 故障過(guò)濾SCL |
| 24-27 FILTSDA | 故障過(guò)濾SDA |
3.10、?Master Configuration Register 3 (MCFGR3)
| 8-19 PINLOW | 低電平超時(shí)時(shí)間 |
3.11、Master Data Match Register (MDMR)
匹配0/1的值
3.12、Master Clock Configuration Register 0 (MCCR0/1)
| 0-5 CLKLO | 時(shí)鐘低電平周期 |
| 0-5 CLKHI | 時(shí)鐘高電平周期 |
| 16-21 SETHOLD | 啟動(dòng)延時(shí) |
| 24-29 DATAVD | 數(shù)據(jù)有效延時(shí) |
3.13、Master FIFO Control Register (MFCR)
接收和發(fā)送的FIFO 水印配置
3.14、Master FIFO Status Register (MFSR)
接收和發(fā)送的FIFO計(jì)數(shù)
3.15、Master Transmit Data Register (MTDR)
| 0-7 DATA | 發(fā)送數(shù)據(jù) |
| 8-10 CMD | 數(shù)據(jù)命令 |
3.16、Master Receive Data Register (MRDR)
| 0-7 DATA | 接收數(shù)據(jù) |
| 14 RXEMPTY | 接收FIFO是否為空 |
3.17、Slave Control Register (SCR)
3.18、Slave Status Register (SSR)
3.19、Slave Interrupt Enable Register (SIER)
3.20、Slave Interrupt Enable Register (SIER)
3.21、Slave Configuration Register 1 (SCFGR1)
3.22、Slave Configuration Register 2 (SCFGR2)
3.23、Slave Address Match Register (SAMR)
3.24、Slave Address Status Register (SASR)
3.25、Slave Transmit ACK Register (STAR)
3.26、Slave Transmit Data Register (STDR)
3.27、Slave Receive Data Register (SRDR)
從機(jī)與主機(jī)基本一樣的內(nèi)容
4、代碼搬運(yùn)工
void LPI2C_init(void) {/* Clk src: SIRCDIV2_CLK* Enable clock for LPI2C0 */PCC->PCCn[PCC_LPI2C0_INDEX] |= PCC_PCCn_PCS(2)| PCC_PCCn_CGC_MASK;/* Prescale = 4* Ignore NACK */LPI2C0->MCFGR1 = LPI2C_MCFGR1_PRESCALE(2)|LPI2C_MCFGR1_IGNACK_MASK;/* SCL_freq = Input_freq / (2^PRESCALER * (CLKLO + CLKHI + 2)) */LPI2C0->MCCR0 = LPI2C_MCCR0_CLKLO(18)| LPI2C_MCCR0_CLKHI(6)| LPI2C_MCCR0_SETHOLD(6)| LPI2C_MCCR0_DATAVD(3);/* Transmitter Water mark set to 0* Receiver Water mark set to 3 */LPI2C0->MFCR = LPI2C_MFCR_TXWATER(0)|LPI2C_MFCR_RXWATER(3);/* Enable LPI2C as master */LPI2C0->MCR |= LPI2C_MCR_MEN_MASK| LPI2C_MCR_DBGEN_MASK; }void LPI2C_Transmit (void) {LPI2C0->MTDR = (0x05<<8)|((0x1E<<1)|0); }?
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