CMOS中的 latch-up 閂鎖效應、添加tap解決latch-up、使用combained area繪制TAP TAP的作用 IC后端版圖【VLSI】

• 一、latch-up、Tap
• • 1. CMOS基礎認知：N-Well和P-Substrate在CMOS里的位置
  • 2. latch-up issue
  • • Latch-up 三種解決方案Prevention
  • 3. 添加tap cells解決latch-up問題
  • 3. TAP的基礎概念
  • • n-well tap & p-substrate tap的工藝規則
    • 排列的個數
• 二、畫版圖layout時的TAP
• • 1. Magic
  • • n-well tap
    • p-substrate tap
  • combained area 分層畫法的解釋：combined contact and tap
  • 2.L-edit
  • • n-substrate tap
    • p-well tap
  • 3. 畫完tap后的自檢
• 三、Reference

一、latch-up、Tap

??本文詳細闡述了latch-up問題、如何通過添加Tap來解決。

1. CMOS基礎認知：N-Well和P-Substrate在CMOS里的位置

??如下圖所示，在N-well里的是NMOS，下圖左邊是NMOS，N-well與 其他p-substrate 隔離分開。

??以PMOS舉例，在PMOS的N-well里，N-well和經過P-type Diffusion后的P-active(下圖中的p+)形成了一個PN結。為了把這個PN結反向偏置形成二極管隔離區域，我們把N-Well連接到高電壓的VDD上，同時把P-Substrate連接到低電壓GND上。。

??但在工作期間，電荷會在 N-well中積聚。這種電荷會改變 P 溝道器件的電位差，從而可能導通這個PN結被正向偏置(Forwad Bias)。如果上面提到的PN結被導通的話，會形成Latch-Up效應，從而損壞整個芯片。

2. latch-up issue

• Latch Up is the Formation of low impedance path from Supply(VDD) to Ground(VSS) due to back to back connected parasitic Bipolar Junction Transistors(BJTs).These BJTs form Silicon Controlled Rectifier(SCR) with positive feedback and short the power and ground rail.
• Latch up comes due high nwell and pwell resistance, Due which potential difference creates that can on the internal transistors.latch-up establish low resistance conducting path between VDD (Supply) and GND (ground), which causes heavy current flow from VDD to GND.
• latch-up establish low resistance conducting path between VDD (Supply) and GND (ground), which causes heavy current flow from VDD to GND.
  

Latch-up 三種解決方案Prevention

• Guard ring. (Decrease the resistance )
• tap cells. (Decrease the resistance)
• Isolation trench. ( avoid undesired current leakage/ current conductive path)

3. 添加tap cells解決latch-up問題

??Silicon substrate and well themselves in fact are relatively highly doped material, but for a good (low-ohmic) contact to metal you want it even higher doped - that’s why these Si-Metal contact regions get additional high(+) implant doses.

??To avoid latch-up, p-substrate-tap (tied to Gnd) and n-well-tap (tied to Vdd) are inserted as frequently as possible. This has the effect of shorting out Rwell and Rsub. 從而阻止避免VDD直接相連到 GND的大電流導通。

3. TAP的基礎概念

??Think of what a faucet(Water Tap) looks like, which injected higher doping to Silicon substrate and well, provide a low-ohmic contact with the metal.

• p-substrate-taps and n-well-taps is concernign on the doping level, proper doping level will lead to gain less than 1 and preveting the current to increase
• Tap cells provide extra dopping of nwell, which lower the resistance.

n-well tap & p-substrate tap的工藝規則

??這里的tap，指的是一塊區域不單只一個東西。指的是，在n-well表面的一塊區域，更深地摻雜n+離子（n-diffusion，版圖里叫n-substratendiff），然后通過metal金屬接到vdd/gnd
形象的解釋見后文版圖畫法
??The N-type material in the well is fairly resistive, so to ensure good control of potential multiple taps are needed for each N-well spread throughout the area.

• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor
  connection (parasitic diode)
• Use heavily doped well and substrate contacts

??In a similar way, P+ substrate taps are added to the P-type substrate to control charge build-up in the substrate.

排列的個數

??The process design rule manual (DRM) will specify a maximum distance between taps to avoid latch-up, but taps need to be inserted far more frequently to ensure good operation of an analog circuit.
??經驗法則：每 5-10 個晶體管放一個tap。

二、畫版圖layout時的TAP

??Physical only cells是那些在網表中沒有，而在實際芯片中需要存在的一些單元，如電源地IO、給IO供電的IO以及一些襯底、阱接觸單元等。這里的TAP就是一種Physical only cells。

??只是物理設計，并不是邏輯器件，可以用combained area這種畫法繪制版圖layout。

1. Magic

magic里：

n-well tap

• nwt是n-well tap，也叫nsubstratencontact
  如前文所述，要摻雜地更濃，添加比較高的摻雜，在n-well區再加n，然后蓋上metal1.
  ps，雖然說，只是為了摻雜的更濃。我個人的理解，在用Magic軟件畫版圖的時候需要把tap區域標清楚，就是需要有實心有對角線的nwt或pst，
  

圖1 在上面未蓋metal1

圖2 蓋了metal1

p-substrate tap

• pst 是p-substrate tap也叫psubstratencontact
  如前文所述，要摻雜地更濃，在p-sub區再加p，然后蓋上metal1.

圖1 在上面未蓋metal1

圖2 蓋了metal1

combained area 分層畫法的解釋：combined contact and tap

??如上所展示，光在GND/VDD的電源軌道上“點”一個tap也可以，但是有的要求會要求畫全。只能用于棒狀圖中diffusion末端與電源或接地軌的觸點重合的情況（變成實心矩形）。注意這里，紅色是polyscilion，藍色是metal1，綠色是n-diffusion，粉紅色是p-substrate，推斷出是個NMOS。

??We can often save space by using a combined contact and tap. Here the tap shares the same Active Area as the contact. A combined contact and tap is defined using a filled black square in place of the source contact (filled black circle).

??A combined contact and tap can only be used where the end of a diffusion stick coincides with a contact to the power or ground rail.

引用： https://secure.ecs.soton.ac.uk/notes/bim/notes/cad/guides/sticks.html

2.L-edit

==本例子是在P阱工藝下，即基底是N型的substrate襯底。==注意看這里沒有n-well

n-substrate tap

在n-implement上增設active-area，然后加上TAP。如前文所述，要摻雜地更濃，在n-sub區再加n-imple，然后蓋上metal1.

p-well tap

由于基底是n型材料，所以需要在底部加P-well。在p-implement上增設active-area，然后加上TAP。如前文所述，要摻雜地更濃，在p-well區再加p-imple，然后蓋上metal1.

3. 畫完tap后的自檢

The following (process independent) guidelines should be considered when deciding on a cell layout.

• For simple functionality we require only one tap per N well and a single tap forthe whole wafer substrate
• Every well must have an appropriate tap.
• Every tap must be connected to a supply pad via unbroken metal.
• Taps should be placed as close to source connections as possible.
• Empirical rule: one tap for every 5-10 transistors.
• Layout N devices packed towards Vss and P devices packed towards Vdd.

三、Reference

wiki

Analog layout – Wells, Taps, and Guard rings

【這個講的很細】PHYSICAL ONLY CELLS

VLSI Design Rules

CMOS中的閂鎖及其預防

數字ASIC設計概要：Tap Cell

Latch-up

Well Tap Cells in Physical Design

Analog layout: Why wells, taps, and guard rings are crucial

芯片設計中的latch_Latch-up （閂鎖效應）

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