使用vivado进行逻辑开发时,进行到Generate Bitstream时报错
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使用vivado进行逻辑开发时,进行到Generate Bitstream时报错
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[Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 4 out of 142 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. ?To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. ?NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. ?Problem ports: USBIND_0_port_indctl[1:0], USBIND_0_vbus_pwrfault, USBIND_0_vbus_pwrselect.
usb接口我沒有使用,drc時檢測沒有約束,導致報錯。根據上述提示將以下保存成tcl文件。
set_property SEVERITY {Warning} [get_drc_checks NSTD-1] set_property SEVERITY {Warning} [get_drc_checks RTSTAT-1] set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
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