開發環境

IAR7.8 + S32K144-EVB

關于FTM的使用，參考了AN5413.pdf中的例程

首先是端口初始化，使用PTD15和PTD16引腳：

void PORT_init(void) {PCC->PCCn[PCC_PORTD_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTD */PORTD->PCR[15]|=PORT_PCR_MUX(2); /* Port D15: MUX = ALT2, FTM0CH0 red */PORTD->PCR[16]|=PORT_PCR_MUX(2); /* Port D16: MUX = ALT2, FTM0CH1 green */ }

然后是FTM模塊初始化:

void FTM0_init(void) {PCC->PCCn[PCC_FTM0_INDEX] &= ~PCC_PCCn_CGC_MASK; /* Ensure clk disabled for config */PCC->PCCn[PCC_FTM0_INDEX] |= PCC_PCCn_PCS(1) | PCC_PCCn_CGC_MASK;/* Clock Src=1, 8 MHz SOSCDIV1_CLK *//* Enable clock for FTM regs */FTM0->MODE |= FTM_MODE_WPDIS_MASK; /* Write protect to registers disabled (default) */FTM0->SC |= FTM_SC_PWMEN1_MASK | FTM_SC_PWMEN0_MASK | FTM_SC_PS(7);/* Enable PWM channel 0,1 output*//* TOIE (Timer Overflow Interrupt Ena) = 0 (default) *//* CPWMS (Center aligned PWM Select) = 0 (default, up count) *//* CLKS (Clock source) = 0 (default, no clock; FTM disabled) *//* PS (Prescaler factor) = 7. Prescaler = 128 */FTM0->COMBINE = 0x00000000;/* FTM mode settings used: DECAPENx, MCOMBINEx, COMBINEx=0 */FTM0->POL = 0x00000000; /* Polarity for all channels is active high (default) */FTM0->MOD = 62500 -1 ; /* FTM1 counter final value (used for PWM mode) *//* FTM1 Period = MOD-CNTIN+0x0001 ~= 62500 ctr clks *//* 8MHz / 128 = 62500Hz -> ticks -> 1Hz */FTM0->SC |= FTM_SC_CPWMS_MASK; }void FTM0_CH0_init(void) {FTM0->CONTROLS[0].CnSC = 0x00000008;FTM0->CONTROLS[0].CnV = 31250; }void FTM0_CH1_init(void) {FTM0->CONTROLS[1].CnSC = 0x00000008;FTM0->CONTROLS[1].CnV = 31250; }void start_FTM0_counter(void) {FTM0->SC |= FTM_SC_CLKS(3);/* Start FTM0 counter with clk source = external clock (SOSCDIV1_CLK)*/ }

注意，在CPWM模式時，CnV的值不能超過0x7FFF:

全部示例代碼如下：

#include "S32K144.h" #include "S32K144_features.h" #include "fsl_core_cm4.h"#define BIT(n) (1 << (n)) #define UNUSED(x) ((void)(x)) #define do_nothing() {static u32 cnt = 0;cnt ++;} #define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))typedef unsigned char u8; typedef unsigned short u16; typedef unsigned long u32;void SOSC_init_8MHz(void); void SPLL_init_160MHz(void); void NormalRUNmode_80MHz(void); void PORT_init(void); void FTM0_init(void); void FTM0_CH0_init(void); void FTM0_CH1_init(void); void start_FTM0_counter(void);int main(void) {SOSC_init_8MHz(); /* Initialize system oscillator for 8 MHz xtal */SPLL_init_160MHz(); /* Initialize SPLL to 160 MHz with 8 MHz SOSC */NormalRUNmode_80MHz(); /* Init clocks: 80 MHz SPLL & core, 40 MHz bus, 20 MHz flash */FTM0_init(); /* Init FTM0 */FTM0_CH0_init(); /* Init FTM0 CH0 */FTM0_CH1_init(); /* Init FTM0 CH1 */PORT_init(); /* Configure ports */start_FTM0_counter(); /* Start FTM0 counter */for(;;) {do_nothing();} }void SOSC_init_8MHz(void) {SCG->SOSCDIV=0x00000101; /* SOSCDIV1 & SOSCDIV2 =1: divide by 1 */SCG->SOSCCFG=0x00000024; /* Range=2: Medium freq (SOSC between 1MHz-8MHz)*//* HGO=0: Config xtal osc for low power *//* EREFS=1: Input is external XTAL */while(SCG->SOSCCSR & SCG_SOSCCSR_LK_MASK); /* Ensure SOSCCSR unlocked */SCG->SOSCCSR=0x00000001; /* LK=0: SOSCCSR can be written *//* SOSCCMRE=0: OSC CLK monitor IRQ if enabled *//* SOSCCM=0: OSC CLK monitor disabled *//* SOSCERCLKEN=0: Sys OSC 3V ERCLK output clk disabled *//* SOSCLPEN=0: Sys OSC disabled in VLP modes *//* SOSCSTEN=0: Sys OSC disabled in Stop modes *//* SOSCEN=1: Enable oscillator */while(!(SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK)); /* Wait for sys OSC clk valid */ }void SPLL_init_160MHz(void) {while(SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK); /* Ensure SPLLCSR unlocked */SCG->SPLLCSR = 0x00000000; /* SPLLEN=0: SPLL is disabled (default) */SCG->SPLLDIV = 0x00000302; /* SPLLDIV1 divide by 2; SPLLDIV2 divide by 4 */SCG->SPLLCFG = 0x00180000; /* PREDIV=0: Divide SOSC_CLK by 0+1=1 *//* MULT=24: Multiply sys pll by 4+24=40 *//* SPLL_CLK = 8MHz / 1 * 40 / 2 = 160 MHz */while(SCG->SPLLCSR & SCG_SPLLCSR_LK_MASK); /* Ensure SPLLCSR unlocked */SCG->SPLLCSR = 0x00000001; /* LK=0: SPLLCSR can be written *//* SPLLCMRE=0: SPLL CLK monitor IRQ if enabled *//* SPLLCM=0: SPLL CLK monitor disabled *//* SPLLSTEN=0: SPLL disabled in Stop modes *//* SPLLEN=1: Enable SPLL */while(!(SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK)); /* Wait for SPLL valid */ }void NormalRUNmode_80MHz(void) {/* Change to normal RUN mode with 8MHz SOSC, 80 MHz PLL*/SCG->RCCR=SCG_RCCR_SCS(6) | SCG_RCCR_DIVCORE(1) | SCG_RCCR_DIVBUS(1) | SCG_RCCR_DIVSLOW(2);/* PLL as clock source*//* DIVCORE=1, div. by 2: Core clock = 160/2 MHz = 80 MHz*//* DIVBUS=1, div. by 2: bus clock = 40 MHz*//* DIVSLOW=2, div. by 3: SCG slow, flash clock= 26 2/3 MHz*/while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 6) {}/* Wait for sys clk src = SPLL */ }void PORT_init(void) {PCC->PCCn[PCC_PORTD_INDEX ]|=PCC_PCCn_CGC_MASK; /* Enable clock for PORTD */PORTD->PCR[15]|=PORT_PCR_MUX(2); /* Port D15: MUX = ALT2, FTM0CH0 red */PORTD->PCR[16]|=PORT_PCR_MUX(2); /* Port D16: MUX = ALT2, FTM0CH1 green */ }void FTM0_init(void) {PCC->PCCn[PCC_FTM0_INDEX] &= ~PCC_PCCn_CGC_MASK; /* Ensure clk disabled for config */PCC->PCCn[PCC_FTM0_INDEX] |= PCC_PCCn_PCS(1) | PCC_PCCn_CGC_MASK;/* Clock Src=1, 8 MHz SOSCDIV1_CLK *//* Enable clock for FTM regs */FTM0->MODE |= FTM_MODE_WPDIS_MASK; /* Write protect to registers disabled (default) */FTM0->SC |= FTM_SC_PWMEN1_MASK | FTM_SC_PWMEN0_MASK | FTM_SC_PS(7);/* Enable PWM channel 0 output*//* TOIE (Timer Overflow Interrupt Ena) = 0 (default) *//* CPWMS (Center aligned PWM Select) = 0 (default, up count) *//* CLKS (Clock source) = 0 (default, no clock; FTM disabled) *//* PS (Prescaler factor) = 7. Prescaler = 128 */FTM0->COMBINE = 0x00000000;/* FTM mode settings used: DECAPENx, MCOMBINEx, COMBINEx=0 */FTM0->POL = 0x00000000; /* Polarity for all channels is active high (default) */FTM0->MOD = 62500 -1 ; /* FTM1 counter final value (used for PWM mode) *//* FTM1 Period = MOD-CNTIN+0x0001 ~= 62500 ctr clks *//* 8MHz / 128 = 62500Hz -> ticks -> 1Hz */FTM0->SC |= FTM_SC_CPWMS_MASK; }void FTM0_CH0_init(void) {//mode selectFTM0->CONTROLS[0].CnSC = 0x00000008;/* FTM0 ch0 compare value (~50% duty cycle) */FTM0->CONTROLS[0].CnV = 31250; }void FTM0_CH1_init(void) {//mode selectFTM0->CONTROLS[1].CnSC = 0x00000008;/* FTM0 ch1 compare value (~50% duty cycle) */FTM0->CONTROLS[1].CnV = 31250; }void start_FTM0_counter(void) {FTM0->SC |= FTM_SC_CLKS(3);/* Start FTM0 counter with clk source = external clock (SOSCDIV1_CLK)*/ }

編譯運行，即可見LED燈以1s的周期閃爍黃色燈光

總結

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