使用AXI VIP發(fā)送transaction的時(shí)候，發(fā)現(xiàn)transaction的每個(gè)beat的wstrb按照右對(duì)齊的方式設(shè)置（data同樣也是按照右對(duì)齊的方式設(shè)置），而不需要按照axi協(xié)議規(guī)定的方式設(shè)置，就可以正確的發(fā)送。這是為什么？

axi協(xié)議關(guān)于wstrb的規(guī)定

These equations determine which byte lanes to use for the first transfer in a burst:
? Lower_Byte_Lane = Start_Address – (INT(Start_Address / Data_Bus_Bytes)) × Data_Bus_Bytes
? Upper_Byte_Lane = Aligned_Address + (Number_Bytes – 1) – (INT(Start_Address / Data_Bus_Bytes)) × Data_Bus_Bytes.

These equations determine which byte lanes to use for all transfers after the first transfer in a burst:
? Lower_Byte_Lane = Address_N – (INT(Address_N / Data_Bus_Bytes)) × Data_Bus_Bytes
? Upper_Byte_Lane = Lower_Byte_Lane + Number_Bytes – 1.

假如要發(fā)送的transaction的addr = 32'h2，burst_size = 32bit，burst_length=4，總線位寬128bit。按照上面的公式，4個(gè)beat的wstrb分別為：16'h000c, 16'h00f0, 16'h0f00, 16'hf000。但是對(duì)于vip來(lái)說(shuō)，即使4個(gè)beat全部配置成16‘hf，vip仍然可以按照上面的公式規(guī)定的方式發(fā)送。

VIP中關(guān)于wstrb的解釋

/*** @groupname axi3_protocol* Array of Write strobes.* If svt_axi_port_configuration::wysiwyg_enable is set to 0 (default), the* wstrb must be stored right-justified by the user. The model will drive* these strobes on the correct lanes.* If svt_axi_port_configuration::wysiwyg_enable is set to 1, the wstrb is * transmitted as programmed by user and is reported as seen on bus. * No right-justification is used in this case.*/rand bit [`SVT_AXI_WSTRB_WIDTH - 1:0] wstrb[]; /*** @groupname axi3_4_config* Acronym for "What You See is What You Get". Applicable to the* svt_axi_transaction::data and svt_axi_transaction::wstrb fields of a* transaction. If this bit is set to 1, whatever is configured in the* svt_axi_transaction::data and svt_axi_transaction::wstrb fields is* transmitted "as is" by the master. Also, in the transaction object* generated by monitor, the monitor populates the svt_axi_transaction::data* and svt_axi_transaction::wstrb fields "as is", as seen on the bus. If* this bit is set to 0 (default), the data must be stored right-justified by* the user. The model will drive the data on the correct lanes.** Refer to the documentation of svt_axi_transaction::data and * svt_axi_transaction::wstrb for more details*/rand bit wysiwyg_enable = 0;

當(dāng)wysiwyg_enable==0的時(shí)候，wstrb采用右對(duì)齊的方式進(jìn)行存儲(chǔ)，所以上述wstrb的后3個(gè)beat配置成16’hf可以正確發(fā)送。第一個(gè)beat是非對(duì)齊的地址，按照右對(duì)齊的方式wstrb應(yīng)該是16’h3，為什么配置成16‘hf也可以正確的發(fā)送呢？

這個(gè)問(wèn)題但是還沒(méi)有找到答案，可能和下面這個(gè)函數(shù)有關(guān)，后續(xù)搞清楚了再更新：

/*** Ensures that only valid lanes have wstrb asserted. In wysisyg format* the constraints leave data[] and wstrb[] open. This function is called in* post_randomize to make sure that wstrb is asserted only for valid lanes*/ extern function void get_wstrb_for_wysiwyg_format(ref bit[`SVT_AXI_MAX_DATA_WIDTH/8-1:0] wstrb[]);

另外，可以使用check_wstrb函數(shù)檢查wstrb：

/** Returns '1' if write strobes are driven correctly otherwise, returns '0' */extern virtual function bit check_wstrb(bit silent=0);

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