FPGA實現(xiàn)FIR濾波

什么是FIR濾波？

FIR(Finite Impulse Response) Filter:有限沖激響應濾波器。
FIR濾波器這里就不贅述其原理了，晚上有很多解釋的。我這里給兩個我參考的，并且認為還不錯的

一個視頻教你理解兩種數(shù)字濾波器，學數(shù)字信號處理必看

FIR數(shù)字信號濾波器

FIR濾波器的verilog實現(xiàn)

源代碼

`timescale 1ns / 1ps // // Company: // Engineer: // // Create Date: 2022/05/10 10:23:52 // Design Name: // Module Name: FIR // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //module FIR(input clk,input rst_n,input [DATA_WIDTH:1] data_in,output reg [DATA_WIDTH + 8:1] filtered_data,output reg filtered_data_valid ); //定義parameterparameter DATA_WIDTH = 8; //數(shù)據(jù)位寬parameter b0 = 0; //FIR抽頭參數(shù)parameter b1 = 8;parameter b2 = 22;parameter b3 = 38;parameter b4 = 50;parameter b5 = 38;parameter b6 = 22;parameter b7 = 8;parameter b8 = 0; //將數(shù)據(jù)緩存reg [DATA_WIDTH:1] data_reg [9:0];integer i,j;always @(posedge clk or negedge rst_n) beginif (!rst_n) beginfor (i = 0;i <=9 ;i = i + 1 ) begindata_reg[i] <= 0;endendelse begindata_reg[0] <= data_in;for (j = 1; j <= 9 ;j = j + 1) begindata_reg[j] <= data_reg[j-1];endendend//進行FIR處理always @(posedge clk or negedge rst_n) beginif (!rst_n) beginfiltered_data <= 0;filtered_data_valid <= 0;endelse beginfiltered_data <= b0 * data_reg[0] + b1 * data_reg[1] + b2 * data_reg[2] + b3 * data_reg[3] + b4 * data_reg[4] + b5 * data_reg[5] + b6 * data_reg[6] + b7 * data_reg[7] + b8 * data_reg[8];filtered_data_valid <= 1;endendendmodule

測試代碼

MATLAB生成信號源

clc; clear all;s_p = 0:255; %正弦波一個周期的采樣點 N = 2^8; sin_data = sin(2*pi*s_p/N);%生成噪聲信號 y2=randn(1, N);%生成一個白噪聲數(shù)組(白噪聲的隨機數(shù)范圍是[-3,3])，數(shù)組長度為N subplot(3,1,2); plot(1:N, y2);%生成正弦波信號和噪聲信號復合的信號 y=sin_data+y2/10; subplot(3,1,3); plot(1:N, y);%定點化 fix_y = fix(y*127) + 150; plot(1:N,fix_y);%寫到文件 fid = fopen('sin_sp_ram_256X8.coe','wt'); fprintf(fid,'MEMORY_INITIALIZATION_RADIX=10;\n'); fprintf(fid,'MEMORY_INITIALIZATION_VECTOR=\n'); for i=1:1:Nfprintf(fid, "%d",fix_y(i));if i == Nfprintf(fid,';');else fprintf(fid,',\n');end end fclose(fid);

Testbench

當然，抽頭數(shù)據(jù)是隨便設的

`timescale 1ns / 1ps // // Company: // Engineer: // // Create Date: 2022/05/10 21:27:44 // Design Name: // Module Name: FIR_tb // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // //module FIR_tb;// Parameterslocalparam DATA_WIDTH = 32;localparam b0 = 0;localparam b1 = 0;localparam b2 = 1;localparam b3 = 3;localparam b4 = 8;localparam b5 = 3;localparam b6 = 1;localparam b7 = 0;localparam b8 = 0;// Portsreg clk = 0;reg rst_n = 0;wire [DATA_WIDTH:1] data_in;wire [DATA_WIDTH:1] filtered_data;wire filtered_data_valid;FIR #(.DATA_WIDTH(DATA_WIDTH ),.b0(b0 ),.b1(b1 ),.b2(b2 ),.b3(b3 ),.b4(b4 ),.b5(b5 ),.b6(b6 ),.b7(b7 ),.b8(b8 ))FIR_dut (.clk (clk ),.rst_n (rst_n ),.data_in (data_in ),.filtered_data (filtered_data ),.filtered_data_valid ( filtered_data_valid));reg [7:0] addra; always @(posedge clk or negedge rst_n) beginif (!rst_n) beginaddra <= 0;endelse beginaddra <= addra + 1; end endwire [31:0] douta; //調(diào)用FIFOFIR_tb_ram your_instance_name (.clka(clk), // input wire clka.wea(0), // input wire [0 : 0] wea.addra(addra), // input wire [7 : 0] addra.dina(0), // input wire [31 : 0] dina.douta(douta) // output wire [31 : 0] douta ); assign data_in[DATA_WIDTH:1] = douta[31:0];initial beginbegin#500 rst_n = 1;endendalways#5 clk = ! clk ;endmodule

測試波形

總結(jié)

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