verilog 多路選擇器 multiplexer

自己寫了一個多路選擇器，寫的端口數(shù)量太多，所以是用來看行為級仿真的。

// An highlighted block module multiplexer36_1( input clk, input rst_n, input [7:0]command,input [31:0]ad_1 , input [31:0]ad_2 , input [31:0]ad_3 , input [31:0]ad_4 , input [31:0]ad_5 , input [31:0]ad_6 , input [31:0]ad_7 , input [31:0]ad_8 , input [31:0]ad_9 , input [31:0]ad_10, input [31:0]ad_11, input [31:0]ad_12, input [31:0]ad_13, input [31:0]ad_14, input [31:0]ad_15, input [31:0]ad_16, input [31:0]ad_17, input [31:0]ad_18, input [31:0]ad_19, input [31:0]ad_20, input [31:0]ad_21, input [31:0]ad_22, input [31:0]ad_23, input [31:0]ad_24, input [31:0]ad_25, input [31:0]ad_26, input [31:0]ad_27, input [31:0]ad_28, input [31:0]ad_29, input [31:0]ad_30, input [31:0]ad_31, input [31:0]ad_32, input [31:0]ad_33, input [31:0]ad_34, input [31:0]ad_35, input [31:0]ad_36,output reg [31:0]data_out);always@(posedge clk or negedge rst_n) if(!rst_n)data_out <= 32'd0; else begin case(command)8'd1 : begin data_out <= ad_1 ;end8'd2 : begin data_out <= ad_2 ;end8'd3 : begin data_out <= ad_3 ;end8'd4 : begin data_out <= ad_4 ;end8'd5 : begin data_out <= ad_5 ;end8'd6 : begin data_out <= ad_6 ;end8'd7 : begin data_out <= ad_7 ;end8'd8 : begin data_out <= ad_8 ;end8'd9 : begin data_out <= ad_9 ;end8'd10 : begin data_out <= ad_10;end8'd11 : begin data_out <= ad_11;end8'd12 : begin data_out <= ad_12;end8'd13 : begin data_out <= ad_13;end8'd14 : begin data_out <= ad_14;end8'd15 : begin data_out <= ad_15;end8'd16 : begin data_out <= ad_16;end8'd17 : begin data_out <= ad_17;end8'd18 : begin data_out <= ad_18;end8'd19 : begin data_out <= ad_19;end8'd20 : begin data_out <= ad_20;end8'd21 : begin data_out <= ad_21;end8'd22 : begin data_out <= ad_22;end8'd23 : begin data_out <= ad_23;end8'd24 : begin data_out <= ad_24;end8'd25 : begin data_out <= ad_25;end8'd26 : begin data_out <= ad_26;end8'd27 : begin data_out <= ad_27;end8'd28 : begin data_out <= ad_28;end8'd29 : begin data_out <= ad_29;end8'd30 : begin data_out <= ad_30;end8'd31 : begin data_out <= ad_31;end8'd32 : begin data_out <= ad_32;end8'd33 : begin data_out <= ad_33;end8'd34 : begin data_out <= ad_34;end8'd35 : begin data_out <= ad_35;end8'd36 : begin data_out <= ad_36;enddefault: begin data_out <= 32'd0;end endcase endendmodule

在圖中可看到，當(dāng)控制命令command改變后，ddata_out的輸出相應(yīng)端口的信號。

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