問題描述：在Vivado生成bit流文件時(shí)，編譯出現(xiàn)問題。
Resource utilization:LUT as Distributed RAM over-utilized in Top Level Design
問題解決：可以嘗試使用URAM來解決BRAM不夠用的問題，從而解決LUT資源的緊張（LUT as Distributed RAM）
從Vivado的報(bào)告可知，對(duì)URAM的利用率為零，那么如何充分利用URAM呢

Arrays on the Interface

在Vivado IP flowVitis HLS中，默認(rèn)情況下將數(shù)組合成為內(nèi)存元素。當(dāng)使用數(shù)組作為頂級(jí)函數(shù)的參數(shù)時(shí)，Vitis HLS假定以下情況之一
1.Memory is off-chip
2.Memory is standard block RAM with a latency of 1
To configure how Vitis HLS creates these ports:
? Specify the interface as a RAM or FIFO interface using the INTERFACE pragma or directive.
? Specify the RAM as a single or dual-port RAM using the storage_typeoption of theINTERFACE pragma or directive.
? Specify the RAM latency using the latencyoption of the INTERFACE pragma or directive.
? Use array optimizationdirectives, ARRAY_PARTITION, or ARRAY_RESHAPE, to reconfigurethe structure of the array and therefore, the number of I/O ports.

Array Interface

如果沒有明確storage_type,Vitis HLS使用：

• A single-port RAM by default
• A dual-port RAM if it reduces the initation interval or reduces
  latency

pragma HLS bind_storage

描述：
BIND_STORAGE pragma將代碼中的變量(數(shù)組或函數(shù)參數(shù))賦給RTL中的特定內(nèi)存類型(type)。
這種用法對(duì)于頂級(jí)函數(shù)接口上的數(shù)組很重要，因?yàn)榕c數(shù)組關(guān)聯(lián)的內(nèi)存類型決定了在theRTL中需要的端口的數(shù)量和類型，如接口上的數(shù)組所討論的
語法：

#pragma HLS bind_storage variable=<variable> type=<type>\ [ impl=<value> latency=<int> ] variable=<variable>:Defines the variable to assign the BIND_STORAGE pragma to. type=<type>: Defines the type of memory to bind to the specified variable. Supported types include: fifo, ram_1p, ram_1wnr, ram_2p, ram_s2p, ram_t2p, rom_1p, rom_2p,rom_np.

impl=<value>: Defines the implementation for the specified memory type. Supportedimplementations include: bram, bram_ecc, lutram, uram, uram_ecc, srl, memory, andauto as described below.

latency=<int>: Defines the default latency for the binding of the type. As shown in thefollowing table, the valid latency varies according to the specifiedtype and impl. The defaultis -1, which lets Vitis HLS choose the latency

Example

#pragma HLS bind_storage variable=coeffs type=RAM_1P impl=bram

the coeffs[128] variable is an argument to the top-level functionfoo_top. The pragma specifies that coeffs uses a single port RAM implemented on a BRAM

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