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Verilog | HDL LCD显示(代码类)
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博主github:https://github.com/MichaelBeechan
博主CSDN:https://blog.csdn.net/u011344545
module lcd(clk, rs, rw, en,dat,switch2); ?
input clk,switch2; ?output [7:0] dat;?output ?rs,rw,en;?reg e;?reg [7:0] dat;?reg rs; ??reg ?[16:0] counter;?reg [4:0] current,next;?reg clkr;?reg [1:0] cnt;?parameter ?set0=4'h0;?parameter ?set1=4'h1;?parameter ?set2=4'h2;?parameter ?set3=4'h3;?parameter ?set4=5'h11;parameter ?set5=5'h1E;parameter ?set6=5'h1F;parameter ?dat0=4'h4;?parameter ?dat1=4'h5;?parameter ?dat2=4'h6;?parameter ?dat3=4'h7;?parameter ?dat4=4'h8;?parameter ?dat5=4'h9;?parameter ?dat6=4'hA;?parameter ?dat7=4'hB;?parameter ?dat8=4'hC;?parameter ?dat9=4'hD;?parameter ?dat10=4'hE;?parameter ?dat11=5'h10;?parameter ?dat12=5'h12;?parameter ?dat13=5'h13;?parameter ?dat14=5'h14;?parameter ?dat15=5'h15;?parameter ?dat16=5'h16;?parameter ?dat17=5'h17;?parameter ?dat18=5'h18;?parameter ?dat19=5'h19;?parameter ?dat20=5'h1A;?parameter ?dat21=5'h1B;?parameter ?dat22=5'h1C;?parameter ?dat23=5'h1D;parameter ?nul=4'hF;?
always @(posedge clk) ? ? ?begin?counter=counter+1;?if(counter==16'h000f) ?clkr=~clkr;?
end?
always @(posedge clkr)?
begin?current=next;?case(current)?set0: ? begin ?rs<=0; dat<=8'h38; next<=set1; end?set1: ? begin ?rs<=0; dat<=8'h0c; next<=set2; end?set2: ? begin ?rs<=0; dat<=8'h6; next<=set3; end?set3: ? begin ?rs<=0; dat<=8'h1; next<=set4; end?set4: ? begin ?rs<=0; dat<=8'h1c; next<=set5; end?set5: ? begin ?rs<=0; dat<=8'h80; next<=dat0; enddat0: ? begin ?rs<=1; dat<="P"; next<=dat1; end?dat1: ? begin ?rs<=1; dat<="l"; next<=dat2; end?dat2: ? begin ?rs<=1; dat<="a"; next<=dat3; end?dat3: ? begin ?rs<=1; dat<="y"; next<=dat4; end?dat4: ? begin ?rs<=1; dat<="i"; next<=dat5; end?dat5: ? begin ?rs<=1; dat<="n"; next<=dat6; end?dat6: ? begin ?rs<=1; dat<="g"; next<=dat7; end?dat7: ? begin ?rs<=1; dat<=" "; next<=dat8; end?dat8: ? begin ?rs<=1; dat<="M"; next<=dat9; end?dat9: ? begin ?rs<=1; dat<="u"; next<=dat10; end?dat10: ? begin ?rs<=1; dat<="s"; next<=dat11; end?dat11: ? begin ?rs<=1; dat<="i"; next<=dat12; end ?dat12: ? begin ?rs<=1; dat<="c"; next<=dat13; end?dat13: ? begin ?rs<=1; dat<="!"; next<=set6; end?set6: ? begin ?rs<=0; dat<=8'hc0; next<=dat14; enddat14: ? begin ?rs<=1; dat<="F"; next<=dat15; end?dat15: ? begin ?rs<=1; dat<="r"; next<=dat16; end?dat16: ? begin ?rs<=1; dat<="i"; next<=dat17; end?dat17: ? begin ?rs<=1; dat<="e"; next<=dat18; end?dat18: ? begin ?rs<=1; dat<="n"; next<=dat19; end?dat19: ? begin ?rs<=1; dat<="d"; next<=dat20; end?dat20: ? begin ?rs<=1; dat<="s"; next<=dat21; end?dat21: ? begin ?rs<=1; dat<="h"; next<=dat22; end?dat22: ? begin ?rs<=1; dat<="i"; next<=dat23; end?dat23: ? begin ?rs<=1; dat<="p"; next<=nul; end?nul: ? begin rs<=0; ?dat<=8'h00; ? ? ? ? ? ? ? ? ? ?//行一遍 然后 把液晶的E 腳 拉高?if(cnt!=2'h2) ?begin ?e<=0;next<=set0;cnt<=cnt+1; ?end ?else ?begin next<=nul; e<=1;?end ? ?end?default: ? next=set0;?endcase?end?
assign en=clkr|e;?
assign rw=0;?
endmodule ?
?
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