一. 模塊功能與應(yīng)用場景

模塊功能：對輸入信號進行降采樣。

應(yīng)用場景：

• 輸入數(shù)據(jù)量太大，后級難以處理，需要減小信號量而不丟失關(guān)鍵信息

二. 模塊框圖與使用說明

參數(shù)DOWN_SAMPLING_TIME控制降采樣倍數(shù)，參數(shù)DIN_WIDTH控制輸入信號位寬。

注意：

din與din_valid應(yīng)對齊

clk應(yīng)就是din與din_valid產(chǎn)生的時鐘，這是為了保證一個有效數(shù)據(jù)din_valid只持續(xù)一個時鐘周期的高電平

三. 模塊代碼

/** @Author : Xu Dakang* @Email : XudaKang_up@qq.com* @Date : 2021-04-21 15:02:16* @LastEditors : Xu Dakang* @LastEditTime : 2021-05-05 15:44:39* @Filename : downSampling.sv* @Description : 降采樣模塊 *//* * 思路: 對din_valid進行計數(shù)，到達DOWN_SAMPLING_TIME輸出一次值 * 注意：1.din與din_valid應(yīng)對齊2.clk應(yīng)就是din與din_valid產(chǎn)生的時鐘，這是為了保證一個有效數(shù)據(jù)din_valid只持續(xù)一個時鐘周期的高電平 */module downSampling #(parameter DOWN_SAMPLING_TIME = 10, // 降采樣倍數(shù)parameter DIN_WIDTH = 24 )(output logic [DIN_WIDTH-1 : 0] down_sampling_dout,output logic down_sampling_dout_valid,input logic [DIN_WIDTH-1 : 0] din,input logic din_valid,input logic clk,input logic rstn );//< 輸入數(shù)據(jù)同步 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ logic [DIN_WIDTH-1 : 0] din_r1; logic [DIN_WIDTH-1 : 0] din_r2; always_ff @(posedge clk) begindin_r1 <= din;din_r2 <= din_r1; endlogic din_valid_r1; logic din_valid_r2; always_ff @(posedge clk) begindin_valid_r1 <= din_valid;din_valid_r2 <= din_valid_r1; end //< 輸入數(shù)據(jù)同步 ------------------------------------------------------------//> 信號計數(shù) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ logic [$clog2(DOWN_SAMPLING_TIME+1)-1 : 0] din_valid_cnt; always_ff @(posedge clk, negedge rstn) beginif (~rstn)din_valid_cnt <= '0;else if (din_valid_r2)if (din_valid_cnt == DOWN_SAMPLING_TIME)din_valid_cnt <= 'd1;elsedin_valid_cnt <= din_valid_cnt + 1'b1;else if (din_valid_cnt == DOWN_SAMPLING_TIME)din_valid_cnt <= '0;elsedin_valid_cnt <= din_valid_cnt; end //> 信號計數(shù) ------------------------------------------------------------//> 輸出降采樣值和有效信號 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ always_ff @(posedge clk, negedge rstn) beginif (~rstn)down_sampling_dout <= '0;else if (din_valid_cnt == DOWN_SAMPLING_TIME)down_sampling_dout <= din_r2;elsedown_sampling_dout <= down_sampling_dout; endalways_ff @(posedge clk, negedge rstn) beginif (~rstn)down_sampling_dout_valid <= 1'b0;else if (din_valid_cnt == DOWN_SAMPLING_TIME)down_sampling_dout_valid <= 1'b1;elsedown_sampling_dout_valid <= 1'b0; end //> 輸出降采樣值和有效信號 ------------------------------------------------------------endmodule

四. testbench

/** @Author : Xu Dakang* @Email : XudaKang_up@qq.com* @Date : 2021-04-21 15:02:16* @LastEditors : Xu Dakang* @LastEditTime : 2021-05-05 15:45:16* @Filename : downSampling_tb.sv* @Description : testbench of downSampling */module downSampling_tb();timeunit 1ns; timeprecision 10ps;localparam DOWN_SAMPLING_TIME = 10; localparam DIN_WIDTH = 24;logic [DIN_WIDTH-1 : 0] down_sampling_dout; logic down_sampling_dout_valid;logic [DIN_WIDTH-1 : 0] din; logic din_valid;logic clk; logic rstn;downSampling #(.DOWN_SAMPLING_TIME (DOWN_SAMPLING_TIME), // 降采樣倍數(shù).DIN_WIDTH (DIN_WIDTH) ) downSampling_inst(.*);// 導(dǎo)入輸入波形文件 string din_path = "F:/OneDrive/VivadoPrj/downSampling/downSampling.srcs/sim_1/new/sinc.txt"; // 可選 sin exp_cos sinclocalparam DATA_NUM = 10000; // 數(shù)據(jù)量, 也就是txt文件的行數(shù), 如果此參數(shù)大于數(shù)據(jù)行數(shù), 讀取到的內(nèi)容為不定態(tài) logic [DIN_WIDTH-1 : 0] din_wave_data [DATA_NUM]; // 讀取輸入波形數(shù)據(jù)initial begin$readmemb(din_path, din_wave_data, 0, DATA_NUM-1); // vivado讀取txt文件 end// 生成時鐘 localparam CLKT = 2; initial beginclk = 0;forever #(CLKT / 2) clk = ~clk; endinitial beginrstn = 0;din_valid = 0;#(CLKT * 10) rstn = 1;for (int i = 0; i < DATA_NUM; i++) begindin = din_wave_data[i];din_valid = 1;#(CLKT);end#(CLKT * 10) $stop; endendmodule

五. 仿真驗證

仿真工具：Vivado 2020.2 Simulator。

輸入為sin信號：

輸入為振蕩信號：

輸入為sinc信號：

六. 工程分享

downSampling 降采樣模塊 vivado 2020.2工程.7z

鏈接：https://pan.baidu.com/s/12-0MQzUJdn9r2WlmgpPzEA
提取碼：bowg

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