一、實(shí)驗(yàn)?zāi)康?/h2>

（1）學(xué)習(xí)并掌握Quartus II的使用方法
（2）學(xué)習(xí)簡(jiǎn)單時(shí)序電路的設(shè)計(jì)和硬件測(cè)試。
（3）學(xué)習(xí)使用VHDL 語(yǔ)言方法進(jìn)行邏輯設(shè)計(jì)輸入
（4）學(xué)習(xí)設(shè)計(jì)8位16進(jìn)制頻率計(jì),學(xué)習(xí)較復(fù)雜的數(shù)字系統(tǒng)設(shè)計(jì)方法，并在實(shí)驗(yàn)開(kāi)發(fā)系統(tǒng)上熟悉運(yùn)行輸入及仿真步驟原理

二、實(shí)驗(yàn)儀器設(shè)備

（1） PC機(jī)一臺(tái)。
（2）Quartus Ⅱ開(kāi)發(fā)軟件一套
（3）EDA實(shí)驗(yàn)開(kāi)發(fā)系統(tǒng)一套(EP1C12Q240C8)

三、實(shí)驗(yàn)原理

頻率計(jì)的工作原理是用一個(gè)頻率穩(wěn)定度高的頻率源作為基準(zhǔn)時(shí)鐘,對(duì)比測(cè)量其他信號(hào)的頻率,也就是周期性信號(hào)在單位時(shí)間內(nèi)變化的次數(shù)。
頻率計(jì)原理如圖所示

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.edge-pattern-dashed{stroke-dasharray:3}#mermaid-svg-ITt1RP1dilxFj5xt .edge-pattern-dotted{stroke-dasharray:2}#mermaid-svg-ITt1RP1dilxFj5xt .marker{fill:#333}#mermaid-svg-ITt1RP1dilxFj5xt .marker.cross{stroke:#333}:root { --mermaid-font-family: "trebuchet ms", verdana, arial;}#mermaid-svg-ITt1RP1dilxFj5xt {color: rgba(0, 0, 0, 0.75);font: ;}被測(cè)信號(hào)閘門(mén)計(jì)數(shù)器數(shù)據(jù)處理與顯示基準(zhǔn)時(shí)鐘門(mén)控信號(hào)

輸入待測(cè)信號(hào)經(jīng)過(guò)脈沖形成電路后形成計(jì)數(shù)的窄脈沖,時(shí)基信號(hào)發(fā)生器產(chǎn)生計(jì)數(shù)閘門(mén)信號(hào),待測(cè)信號(hào)通過(guò)閘門(mén)進(jìn)入計(jì)數(shù)器計(jì)數(shù)，即可得到其頻率。若閘門(mén)開(kāi)啟時(shí)間為T(mén),待測(cè)信號(hào)頻率為$f_x$,在閘門(mén)時(shí)間T內(nèi)計(jì)數(shù)器計(jì)數(shù)值為N，則待測(cè)信號(hào)頻率為$f_x$=N/T。閘門(mén)時(shí)間通常取為1s。
根據(jù)頻率的定義和頻率測(cè)量的基本原理,測(cè)定信號(hào)的頻率必須有一個(gè)脈寬為1s的輸入信號(hào)脈沖計(jì)數(shù)允許的信號(hào);1s計(jì)數(shù)結(jié)束后，計(jì)數(shù)值被鎖入鎖存器，計(jì)數(shù)器清0,為下一測(cè)頻計(jì)數(shù)周期做好準(zhǔn)備。測(cè)頻控制信號(hào)可以由一個(gè)獨(dú)立的發(fā)生器來(lái)產(chǎn)生根據(jù)測(cè)頻原理,測(cè)頻控制時(shí)序如圖所示。設(shè)計(jì)要求是:FTCTRL 的計(jì)數(shù)使能信號(hào)CNT_EN能產(chǎn)生一個(gè)1s 脈寬的周期信號(hào)，并對(duì)頻率計(jì)中的32位二進(jìn)制計(jì)數(shù)器COUNTER32B的 ENABL使能端進(jìn)行同步控制。當(dāng)CNT_EN高電平時(shí)允許計(jì)數(shù)，低電平時(shí)停止計(jì)數(shù)，并保持其所計(jì)的脈沖數(shù)。在停止計(jì)數(shù)期間，首先需要個(gè)鎖存信號(hào)LOAD的上跳沿將計(jì)數(shù)收器在前1s的計(jì)數(shù)值鎖存進(jìn)鎖存器REG32B 中，并由外部的16進(jìn)制7段譯碼器譯出，顯示計(jì)數(shù)值。設(shè)置鎖存器的好處是數(shù)據(jù)顯示穩(wěn)定，不會(huì)由于周期性的清0信號(hào)而不斷閃爍。鎖存信號(hào)后,必須有一清0信號(hào)RST_CNT對(duì)計(jì)數(shù)器進(jìn)行清零,為下1s的計(jì)數(shù)操作做好準(zhǔn)備。

四、實(shí)驗(yàn)內(nèi)容

分別仿真測(cè)試模塊例1、例2和例3,再結(jié)合例4完成頻率計(jì)的完整設(shè)計(jì)和硬件實(shí)現(xiàn),并給出其測(cè)頻時(shí)序波形及其分析。建議選實(shí)驗(yàn)電路模式5；8個(gè)數(shù)碼管以16進(jìn)制形式顯示測(cè)頻輸出;待測(cè)頻率輸入FIN 由 clock0輸入,頻率可4Hz、256Hz、3Hz、…、50MHz等；1Hz測(cè)頻控制信號(hào)CLK1Hz可由 clock2輸入（用跳線選1HZ)。注意，這時(shí)8個(gè)數(shù)碼管的測(cè)控顯示值是16進(jìn)制的。

五、實(shí)驗(yàn)步驟

（1）啟動(dòng)Quartus II建立一個(gè)空白工程,然后命名為 FREQTEST.qpf。
（2）新建VHDL 源程序文件FREQTEST.vhd,輸入程序代碼并保存，進(jìn)行綜合編譯,若編譯過(guò)程中發(fā)現(xiàn)錯(cuò)誤，則找出并更正錯(cuò)誤，直至編譯成功為止。
（3）選擇目標(biāo)器件并對(duì)相應(yīng)的引腳進(jìn)行鎖定,在這里所選擇的器件為Altera公司 Cyclone系列的EPIC12Q240C8芯片。將未使用的管腳設(shè)置為三態(tài)輸入。則找出并更正錯(cuò)誤,
（4）對(duì)該工程文件進(jìn)行全程編譯處理，若在編譯過(guò)程中發(fā)現(xiàn)錯(cuò)誤直至編譯成功為止。接到PC機(jī)的打印機(jī)并口
（5）拿出 Altera Byte Blaster II下載電纜，并將此電纜的兩端分別接到PC機(jī)的打印機(jī)并口和實(shí)驗(yàn)箱的JTAG下載口上，打開(kāi)電源，執(zhí)行下載命令，把程序下載到 FPGA器件中，觀察數(shù)碼管1~8的16進(jìn)制顯示狀態(tài)。
實(shí)例代碼：

LIBRARY IEEE; --頻率計(jì)頂層文件 USE IEEE.STD_LOGIC_1164.all; ENTITY FREQTEST IS PORT(CLK1HZ:IN STD_LOGIC;FSIN:IN STD_lOGIC;DOUT:OUT STD_LOGIC_VECTOR(31 downto 0)); END; ARCHITECTURE BEHAV OF FREQTEST isCOMPONENT FTCTRLPORT(CLKK: IN STD_LOGIC; --1HZCNT_EN: OUT STD_LOGIC; --計(jì)數(shù)器時(shí)鐘使能RST_CNT:OUT STD_LOGIC; --計(jì)數(shù)器清零LOAD : OUT STD_LOGIC); --輸出鎖存信號(hào)END COMPONENT;COMPONENT COUNTER32BPORT(FIN: IN STD_LOGIC; --時(shí)鐘信號(hào)ENABL: IN STD_LOGIC; --清零信號(hào)CLR : IN STD_LOGIC; --計(jì)數(shù)使能信號(hào)DOUT: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); --計(jì)數(shù)結(jié)果輸出END COMPONENT;COMPONENT REG32BPORT(LK: IN STD_LOGIC;DIN: IN STD_LOGIC_VECTOR(31 downto 0);DOUT: OUT STD_LOGIC_VECTOR(31 downto 0));END COMPONENT;SIGNAl TSTEN1: STD_LOGIC;SIGNAl CLR_CNT1:STD_LOGIC;SIGNAl LOAD1: STD_LOGIC;SIGNAl DTO1: STD_LOGIC_VECTOR(31 DOWNTO 0);SIGNAl CARRY_OUT1:STD_LOGIC_VECTOR(6 DOWNTO 0); BEGIN u1: FTCTRL PORT MAP (CLKK=>CLK1HZ,CNT_EN=>TSTEN1,RST_CNT=>CLR_CNT1,LOAD=>LOAD1); --例化 U2: REG32B PORT MAP(LK=>LOAD1,DIN=>DTO1,DOUT=>DOUT); --例化 U3:COUNTER32B PORT MAP(FIN => FSIN,CLR => CLR_CNT1,ENABL=> TSTEN1,DOUT=>DTO1); --例化 END BEHAV; LIBRARY IEEE; --測(cè)頻控制電路 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FTCTRL ISPORT (CLKK : IN STD_LOGIC; --1HZCNT_EN :OUT STD_LOGIC; --計(jì)數(shù)器使能控制RST_CNT:OUT STD_LOGIC; --計(jì)數(shù)器清零端Load: OUT STD_LOGIC ); --輸出鎖存信號(hào) END FTCTRL; ARCHITECTURE BEHAV OF FTCTRL ISSIGNAL Div2CLK : STD_LOGIC; BEGINPROCESS(CLKK)BEGINIF CLKK'EVENT AND CLKK = '1' THEN --1HZ時(shí)鐘2分頻Div2CLK <= NOT Div2CLK;END IF;END PROCESS;PROCESS(CLKK, Div2CLK)BEGINIF CLKK='0' AND Div2CLK='0' THEN RST_CNT<='1'; --產(chǎn)生清零計(jì)數(shù)ELSE RST_CNT <= '0';END IF;END PROCESS;Load <= NOT Div2CLK;CNT_EN <= Div2CLK; END BEHAV; LIBRARY IEEE; --32位鎖存器 USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG32B ISPORT(LK: IN STD_LOGIC; DIN: IN STD_LOGIC_VECTOR(31 downto 0);DOUT: OUT STD_LOGIC_VECTOR(31 downto 0));END REG32B; ARCHITECTURE BEHAV OF REG32B IS BEGINPROCESS(LK,DIN)BEGINIF LK'EVENT AND LK='1' THEN DOUT<=DIN;END IF;END PROCESS; END BEHAV; LIBRARY IEEE; --32位計(jì)數(shù)器 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER32B ISPORT(FIN:IN STD_LOGIC; --時(shí)鐘信號(hào)CLR:IN STD_LOGIC; --清零信號(hào)ENABL:IN STD_LOGIC; --計(jì)數(shù)使能信號(hào)DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COUNTER32B; ARCHITECTURE BEHAV OF COUNTER32B ISSIGNAL CQI : STD_LOGIC_VECTOR(31 DOWNTO 0);BEGINPROCESS(FIN,CLR,ENABL)BEGINIF CLR='1' THEN CQI<=(OTHERS=>'0'); --清零ELSIF FIN'EVENT AND FIN='1' THENIF ENABL='1' THEN CQI<=CQI+1;END IF;END IF;END PROCESS;DOUT<=CQI;END BEHAV;

QUARTUS II代碼展示圖

頻率計(jì)仿真圖如圖所示

六、實(shí)驗(yàn)要求

（1）選擇實(shí)驗(yàn)電路模式5
（2）設(shè)計(jì)仿真文件，進(jìn)行軟件驗(yàn)證
（3）用VHDL程序設(shè)計(jì)方法實(shí)現(xiàn)8位16進(jìn)制頻率計(jì)設(shè)計(jì)
（4）通過(guò)下載線下載到實(shí)驗(yàn)系統(tǒng)上進(jìn)行硬件測(cè)試驗(yàn)證

七、實(shí)驗(yàn)擴(kuò)展

實(shí)驗(yàn)內(nèi)容2:將頻率計(jì)改為8位10進(jìn)制頻率計(jì),注意此設(shè)計(jì)電路的計(jì)數(shù)器必須是8個(gè)4位的10進(jìn)制計(jì)數(shù)器，而不是1個(gè)。此外注意在測(cè)頻速度上給予優(yōu)化。
八位十進(jìn)制頻率計(jì)頂層文件：

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FREQTEST8_10 IS PORT(FSIN:IN STD_LOGIC;CLK1HZ:IN STD_LOGIC;DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END ENTITY FREQTEST8_10; ARCHITECTURE BEHAV OF FREQTEST8_10 IS COMPONENT CNT10 IS PORT(FIN,CLR,ENA:IN STD_LOGIC;CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT:OUT STD_LOGIC); END COMPONENT CNT10; COMPONENT REG32B IS PORT(LOAD:IN STD_LOGIC;DIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0);DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END COMPONENT REG32B; COMPONENT FTCTRL IS PORT(CLKK:IN STD_LOGIC;CNT_EN:OUT STD_LOGIC;RST_CNT:OUT STD_LOGIC;LOAD:OUT STD_LOGIC); END COMPONENT FTCTRL;SIGNAL EN,CL,LD:STD_LOGIC;SIGNAL CNT1,CNT2,CNT3,CNT4,CNT5,CNT6,CNT7,CNT8:STD_LOGIC;SIGNAL DQ:STD_LOGIC_VECTOR(31 DOWNTO 0); BEGINU0:FTCTRL PORT MAP(CLKK=>CLK1HZ,CNT_EN=>EN,RST_CNT=>CL,LOAD=>LD);U1:CNT10 PORT MAP(FIN=>FSIN,CLR=>CL,ENA=>EN,CQ=>DQ(3 DOWNTO 0),COUT=>CNT1);U2:CNT10 PORT MAP(CNT1,CL,EN,DQ(7 DOWNTO 4),CNT2);U3:CNT10 PORT MAP(CNT2,CL,EN,DQ(11 DOWNTO 8),CNT3);U4:CNT10 PORT MAP(CNT3,CL,EN,DQ(15 DOWNTO 12),CNT4);U5:CNT10 PORT MAP(CNT4,CL,EN,DQ(19 DOWNTO 16),CNT5);U6:CNT10 PORT MAP(CNT5,CL,EN,DQ(23 DOWNTO 20),CNT6);U7:CNT10 PORT MAP(CNT6,CL,EN,DQ(27 DOWNTO 24),CNT7);U8:CNT10 PORT MAP(CNT7,CL,EN,DQ(31 DOWNTO 28),CNT8);U9:REG32B PORT MAP(LOAD=>LD,DIN=>DQ(31 DOWNTO 0),DOUT=>DOUT); END ARCHITECTURE BEHAV;

十進(jìn)制計(jì)數(shù)器示例程序：

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CNT10 IS PORT(FIN:IN STD_LOGIC;CLR:IN STD_LOGIC;ENA:IN STD_LOGIC;CQ:OUT INTEGER RANGE 0 TO 15;COUT:OUT STD_LOGIC); END ENTITY CNT10; ARCHITECTURE BEHAV OF CNT10 ISSIGNAL CQI:INTEGER RANGE 0 TO 15;BEGINPROCESS(FIN,CLR,ENA)ISBEGINIF CLR='1'THEN CQI<=0;ELSIF FIN'EVENT AND FIN='1'THENIF ENA='1'THENIF CQI<9 THEN CQI<=CQI+1;ELSE CQI<=0;END IF;END IF;END IF;END PROCESS; PROCESS(CQI) ISBEGINIF CQI=9 THEN COUT<='1';ELSE COUT<='0';END IF;END PROCESS;CQ<=CQI; END ARCHITECTURE BEHAV;

測(cè)頻控制電路示例程序：

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FTCTRL ISPORT (CLKK : IN STD_LOGIC;CNT_EN : OUT STD_LOGIC;RST_CNT : OUT STD_LOGIC;LOAD: OUT STD_LOGIC ); END FTCTRL; ARCHITECTURE BEHAV OF FTCTRL ISSIGNAL Div2CLK : STD_LOGIC; BEGINPROCESS( CLKK )BEGINIF CLKK'EVENT AND CLKK = '1' THENDiv2CLK <= NOT Div2CLK;END IF;END PROCESS;PROCESS(CLKK, Div2CLK)BEGINIF CLKK='0' AND Div2CLK='0' THEN RST_CNT<='1';ELSE RST_CNT <= '0';END IF;END PROCESS;LOAD <= NOT Div2CLK;CNT_EN <= Div2CLK; END BEHAV;

32位鎖存器示例代碼：

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG32B ISPORT(LOAD:IN STD_LOGIC;DIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0);DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END ENTITY REG32B; ARCHITECTURE BEHAV OF REG32B ISBEGINPROCESS(LOAD,DIN) ISBEGINIF LOAD'EVENT AND LOAD='1' THEN DOUT<=DIN;END IF;END PROCESS; END ARCHITECTURE BEHAV;

8位10進(jìn)制頻率計(jì)仿真波形圖

管腳定義實(shí)況：

后續(xù)有時(shí)間會(huì)加更ing…

工程文件下載：
8位16進(jìn)制頻率計(jì)設(shè)計(jì)源代碼
8位10進(jìn)制頻率計(jì)設(shè)計(jì)源代碼

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