week9:

查找論文的情況

1.*(reference) title:Improving Performance and Capacity of Flash Storage Devices by Exploiting Heterogeneity of MLC Flash Memory author:Sungjin Lee ; Jihong Kim from:IEEE TRANSACTIONS ON COMPUTERS content: (1)A MLC NAND flash memory, each memory cell can be programmed as a single-level cell or a multi-level cell at runtime (2)present a flexible flash file system, called FlexFS, (3)To provide high performance and high capacity simultaneously, FlexFS employs a dynamic free-space management (DFM) technique. (4)FlexFS also adopts a novel dynamic lifetime management (DLM) technique, which manages the storage lifetime by controlling the use of SLC-mode programming. (5)In order to achieve the SLC performance, FlexFS writes as many data as possible toflash memory using fast SLC-mode programming. *(6)Free-space reclamation--idle time (7)The dynamic free-space management (DFM) technique resolves the problems caused by improper management of free space by maintaining minimal but sufficient free space (8)The dynamic lifetime management (DLM) technique adaptively controls the wearing rate offlash memory (which is accelerated by free-space reclamation) so that a reasonable storage lifetime can be provided (9)FlexFS is based on a JFFS2file system (10)same pages? (11)2 write buffer & log (12)free-space reclamation is performed only when there are no user I/O activities and on-demand free-space reclamation is not required (see Section 3.2).free-space reclamation is performed only when there are no user I/O activities and on-demand free-space reclamation is not required. (13)If an observed idle period is longer than a certain threshold value, FlexFS triggers free-space reclamation, expecting that there will be a long idle period.[50 ms] (14) delayed freespace reclamation does not trigger free-space reclamation unless available free space is smaller than TH. (15)a delayed free-space reclamation policy that delays free-space reclamation as long as possible so that many data are invalidated in the SLC region. [SLC invalid page] (16)DLM[w]

2. title:A Workload-Aware-Design of 3D-NAND Flash Memory for Enterprise SSDs author:Chao Sun(Japan) from:15th Int'l Symposium on Quality Electronic Design(2014) content: (1)SCM/NAND flash hybrid

3. title:Differentiated Storage Services autor:Michael Mesnier, Feng Chen, Tian Luo from:SOSP '11 content: (1)I/O classification architecture (2)As examples, the “middle” of a disk can be used to reduce seek latency, and the “outer tracks” can be used to improve transfer speeds. (3)I/O is classified as metadata, journal, directory, or file, and file I/O is further classified by the file size (e.g., ≤4KB≤16KB, ...,>1GB). (4)we modify the OS block layer so that every I/O request carries a classifier. We copy this classifier into the I/O command.In this way, a storage system can provide block-level differentiated services (performance,reliability, or security) (5)This paper focuses on priorities (6)Our storage systems implement a priority-based performance policy, so we map each class to a priority level (7)For the FS, the priorities reflect our goal to reduce small random access in the storage system, by giving small files and metadata higher priority than large files. For the DB, we simply demonstrate the flexibility of our approach by assigning caching policies to common data structures (indexes, tables, and logs).

4.* title: Hystor: Making the Best Use of Solid State Drives in High Performance Storage Systems autor: Feng Chen David Koufaty from: ICS’11(2011) content: *(1)針對LRU的缺點改進，缺點（cache pollution problem ） (2)a special data structure, called block table. for large-scale history recode. (3)automatically learns *(4)identifies semantically-critical blocks (e.g. file system metadata) （5）HDD和SDD混合 （6）request size, frequency, seek distance, reuse distance, （7）use the blktrace tool （8）(frequency/request_size）is found to be the most effective one

thought (1)多個優先級維度，比如更新快于寫入？---順序 (2)對比，要比LRU好，也要比size threshold 好，可以從正確分配比例上、page collection上 (3)SLC1：for random ； SLC2：for cache (4)先在SLC中讀寫，然后不用了再調度到TLC中 (5)request size, frequency, // logical move distance, reuse distance, size change // on time requests , on time workload (6)SLC/TLC Range (7)[write paper]---Details Introduction (8)SLC--->TLC idle time[find a suitable time]& 1.14 & 1.15[paper1:3.21,fig7]

?

?

week10:?

Liu review:

I think this is the strategy of your implementation. For the paper, we need to add some therotical things. To prepare this paper, you need to study the "design space exploration", and try to apply this therory into the TLC/SLC flash memory management.

Please look at the following materials. Then you can tell me what is design space exploration.

http://people.csail.mit.edu/eskang/papers/monterey10.pdf http://dse.esi.nl/ google:design space exploration qingfeng zhuge

第一： title：基于模型樹的多核設計空間探索技術 author：郭　崎，陳天石（中國科學院） from:計算機輔助設計與圖形學學報 content: (1)．統計采樣,統計模擬 (2)，其主要目標都是對用于評估模擬的復雜基準測試程序進行精簡，提取（統計采樣）或者構造（統計模擬）出新的程序來代替原程序執行 (3), 本文介紹了基于模型樹的預測模型方法用于復雜多核設計空間探索的問題

第二：* title：Design Space Exploration of Embedded System from：PPT content: （1）“Review of General Aspects”介紹好像和trace file挺相關的，沒有具體算法 （2）“Basic Models and Methods”

第三：(沒看懂) title：Design? Space? Minimization with? Timing? and? Code? Size Optimization? for? Embedded? DSP from：CODES+ISSS'03（2003） content： （1）We show an effective way to reduce the? design space to be explored? through the st udy of the? fundamental properties and relations? among? multiple design parameters,? such? as retiming? value, unfolding factor （2）problems:in high-level synthesis? is? how? to? explore? a? wide? range? of? design options to? achI eve hIgh-quality designs? within a short time （3）retiming?

第四： title：An Approach for Eective Design Space Exploration author：Eunsuk Kang, Ethan Jackson（Massachusetts Institute of Technology, Cambridge） content： （1）定義：Design space exploration (DSE) refers to the activity of exploring design alternatives prior to implementation. 設計空間探索（DSE）是指在執行之前探索設計選擇方案的活性。 （2）用途engineering tasks：rapid prototyping, optimization, and system integration （3）主要挑戰：龐大的design space，枚舉的話太難 （4）key idea：The key idea is that many of the design candidates may be considered equivalent as far as the user is concerned, and so only a small subset of the space needs to be explored.很大一部分是類似的.

（5）Introduction (5.1)應用范圍的具體解釋（rapid prototyping, optimization, and system integration. ） (5.2)結構，必須包含的部分： ?a）Representation:formal ?b) Analysis:(自動分析) ?c) Exploration method:篩選壞結構后數量還是很多，歸納一樣的，選有特色的。 （5.3）solution，interstate？ （6）Motivating Example (6.1)一個圖論的著色問題 (6.2)An optimization problem cannot be formulated easily at this high-level, and so rapid prototyping combined with simulation is the approach that is often taken to evaluate design alternatives (6.3)enumerate枚舉法：each solution in the design space will have a large (possibly innite) number of counterparts that dier only by labeling of devices. （7）Background on FORMULA （7.1）本例中選用CLP語言來描述約束 （7.2）表達式（1）（2） (8)Design Space Exploration Method ?* (8.1)這一節應該是將如何去除 similar solution (8.2)Na}ve Exploration Algorithm:有相同的部分就丟棄 （8.3）第十頁，注解三的算法用來計算等價類 （8.4）Improved Algorithm

?

?

week 12:?

1. title：Phoenix: Reviving MLC Blocks as SLC to Extend NAND Flash Devices Lifetime author：Xavier Jimenez, David Novo and Paolo Ienne from:date 13 content: （1）present Phoenix，a novel scheme to extend current FTL that mitigate the degradation in lifetime of MLC flash. （2）損壞的MLC復活為SLC，增加ECC的編碼長度 （3）統計計算了確定了邊界值

2.這是一個關于電壓和容錯的 title：Estimating Information-Theoretical NAND Flash Memory Storage Capacity and its Implication to Memory System Design Space Exploration author：Guiqiang Dong，Ningde Xie from：IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2012 content： （1）introduction中512/512+28*2=1.9 這個公式有問題 （2）background: （2.1）等式1，擦除電壓成正太分布。 （2.2）[B]Effects of P/E Cycling ? ?(2.3) [C]Cell-to-Cell Interference ?(3) 10K P/E cycling and 10-year retention:當trace數值比較低的時候，轉化成時間，看起來比較長。

3. Jingtong Hu 主頁

4. title：Cross-Architectural Design Space Exploration Tool for Reconfigurable Processors author:Muhammad Shafique from:DATE09 content: 有關不同指令集結構的。

5. title:DESSERT:? DESign? Space? ExploRation? Tool? based on? Power? and? Energy? at? System-Level author:Santhosh? Kumar? Rethinagiri*,? Oscar? Palomar* from:SOCC 2014 content: (1)DSE? tool? at? system-level? to? estimate? power and? energy? consumption? of? an? application? on? a? heteroge-neous? quad-core? platform? consisting? of? ARM Cortex-Al5? and Cortex-A? 7? processors (2)Table2展示了各種內核的能耗公式

6. PPT:Gordon:Using Flash Memory to Build Fast, Powerefficient Clusters for Data-intensive Applications author:Adrian M. Caulfield (University of California, San Diego) (1)將Flash Memory用于數據中心，優化其并行性 *（2）有一些workload 數據 *（3）Write Combining：Merge multiple writes to the same address when possible

?

week13

1. title：Architecture Exploration of NAND Flash-based Multimedia Card author：Sungchan Kim from：DATE08 content： （1）the reduction of cost is a primary design concern ?(2)efficient evolutionary algorithm (3)Previous works:[1][2][3][4]

(4)Memory cards typically consist of only a few bus masters and a small number of memory components *(5)We use TLM simulation only for memory trace generation and use trace-driven simulation for fast but accurate performance estimation in the inner-most exploration loop. 這是一個兩級的策略，對不同trace用不同的策略 （6） The first step is to collect memory traces for a given test scenario The different size of double buffers requires a slight modification of the firmware running on the card. (7) ?Once these parameters are chosen, a TLM simulation is run to get the memory traces. (8) After obtaining memory traces, the bus matrix and memory architecture exploration is performed

2. title：Memory System Design Space Exploration for Low-Power,Real-Time Speech Recognition author：Rajeev Krishna, Scott Mahlke, and Todd Austin（University of Michigan） from：ISSS-CODES’04 content： （1）This work presents a design space exploration of potential memory system architectures （2）We find that moderate sized hybrid Chip Multiprocessor / MultiThreading (CMP/MT) architectures (4) simple pipelines, 2–4 hardware contexts each), combined with multilevel caching targeting program metadata (dynamic programming lists and the like) provide good tradeoffs in maximizing performance while reducing overall energy consumption. (5)應用程序為語音識別

3. title：design space exploration of memory model for heterogeneous computing author：Jieun Lim，Hyesoon Kim from：MSPC’12 content： **（1） MacSim simulator ，a cycle-level and trace-driven simulator for our simulations. http://code.google.com/p/macsim/

4.***write good title：A Workload-Aware Adaptive Hybrid Flash Translation Layer with an Efficient Caching Strategy author：Dongchul Park, Biplob Debnath and David H.C. Du from：10.1109/MASCOTS.2011.29 content： (1)propose a Convertible Flash Translation Layer (it can dynamically switch its mapping scheme to either a page level mapping or a block level mapping scheme to fully exploit the benefits of them) Moreover, we propose an efficient caching strategy to further improve the CFTL performance. (2) block_level mapping:read 為主的trace page_level mapping:write 為主的trace (3) mapping table is stored in the flash memory caching scheme **(4)計算page level map 1 TB of flash requires 4GB of memory space for the mapping table (assuming a 2KB page and 8 bytes per mapping entry) *(4) 引用的23-25，是trace *(5) 有R/W比例列表

?

?

week14

1.white paper Intel SSD DC S3500 Series Workload Characterization in RAID Configurations *（1）page 7，有張表 *（2）page 11, 不同random 比例下性能

2.review SSDExplorer: a Virtual Platform for Performance/Reliabilityoriented Fine-Grained Design Space Exploration of Solid State Drives author:Lorenzo Zuolo, Cristian Zambelli (1) EDA tools ? (2) this paper proposes SSDExplorer *(3)former research disk emulation tools [3] in virtual environments [4] pure software simulation tools[5] [3] J. Yoo, Y. Won, J. Hwang, S. Kang, J. Choi, S. Yoon, and J. Cha,“Vssim: Virtual machine based ssd simulator,” in IEEE Symposium on Mass Storage Systems and Technologies (MSST), 2013, pp. 1–14 [4] “QEMU: open source processor emulator.” [Online]. Available:http://wiki.qemu.org/Main Page [5] “The DiskSim simulation environment version 4.0,” 2008.[Online]. Available:http://www.pdl.cmu.edu/PDL-FTP/DriveChar/CMU-PDL-08-101.pdf (4)比較之前的Emulation Platforms/ Trace driven Platforms /Hardware Platforms,提出SSDExplorer Prenlatform 認為之前的：really miss ： is a clear exploration of the performance correlation between the host interface capabilities and the non-volatile memory subsystem involving all intermediate architectural blocks

3.review***圖片可以參考 title：VSSD: Performance Isolation in a Solid -State Drive author：DA-WEI CHANG, HSIN-HUNG CHEN and WEI-JIAN SU（National Cheng Kung University） form：TODAES-2014

*可以回看一下3.1、3.2，講主要技術

?

week15

1.重讀 title：Estimating Information-TheoreticalNAND Flash Memory Storage Capacity and its Implication to Memory System Design Space Exploration from：TVLSI.2011. content：Guiqiang Dong， Ningde Xie, Chandra Varanasi, and Tong Zhang? （1）1.9 bits/cell 表示 2 bit/cell 的利用率 （2）香濃理論來估計信道噪聲影響 （3）難以準確估計，估計得上下限 （4）tradeoff：cell的利用率和使用壽命 （5）Monte Carlo simulations http://blog.csdn.net/mmbl007/article/details/6204003

2. title：Model-Driven Design-Space Exploration for Software-Intensive Embedded Systems author：Twan Basten, Martijn Hendriks, Lou Somers, and Nikola Trcka from: content： (1)Motivation:Software plays an increasingly important role in modern embedded systems, leading to a rapid increase in design complexity. (2)Industries typically adopt some form of model-based design for the software and hardware embedded in their systems.They provide a quick and easy method to explore alternatives at a high abstraction level. (3)用打印機的一個例子說明Octopus tool有效性。

3. title：Model-Driven Design-Space Exploration for Embedded Systems: The Octopus Toolset author：Twan Basten, Emiel van Benthum from： content： （1）

4. title：A Survey on Exact Cache Design Space Exploration Methodologies for Application Specific SoC Memory Hierarchies author：Isuru Nawinne,Sri Parameswaran from：ICIIS 2013 content： （1）capacity of a cache C：C = (B * S * A)Bytes （2） trace-driven simulation （3） use heuristics and design of experiment methods：avoid exploring the whole design space 接著介紹了幾種cache的處理方法（沒有細看）

5. title：A Survey on Design Space Exploration for Heterogeneous Multi-core author：Meena Belwal, Sudarshan TSB from：ICES 2014(International Conference on Embedded Systems ) content： （1）DSE is the process of discovering and evaluating design alternatives, prior to implementation. （2）圖1 DSE流程圖，以及圖下的文字介紹。 （3）page 2 paragraph 2，介紹了DSE在HW/SW設計中的應用場景。 （4）從第三頁開始，A/B/C/D/ 沒部分第一段都是一類的應用

6. title：A Meta-Framework for Design Space Exploration author：Tripti Saxena and Gabor Karsai from：ECBS.2011.21 content： （1）abstract里有design space的定義 （2）introduce第二段，有不同的DSE的方法 （3）第三部分講了一些設計要求（論文用？）

?

week16

1. title：Configurability of Performance and Overheads in Flash Management author：Tei-Wei Kuo from： content (1)Performance and overheads. (2)

2. title:The Behavior Analysis of Flash-Memory Storage Systems author：Tei-Wei Kuo

轉載于:https://www.cnblogs.com/yaolei/p/4078803.html

總結

以上是生活随笔為你收集整理的weekly paper read的全部內容，希望文章能夠幫你解決所遇到的問題。

如果覺得生活随笔網站內容還不錯，歡迎將生活随笔推薦給好友。