1、器件結(jié)構(gòu)

分離柵VDMOS是在傳統(tǒng)溝槽柵VDMOS的基礎(chǔ)上將柵極分為兩段，底部的柵極和源極接相同電位，從而屏蔽了部分柵漏間的電容。該結(jié)構(gòu)有助于減小Miller電容，提高器件的開關(guān)速度。

2、工藝流程

分離柵VDMOS的簡要工藝流程如下圖所示，實(shí)際工藝中將包含更多細(xì)節(jié)：

1) 襯底---> 2) 外延---> 3) 表面氧化---> 4) 光刻氧化層定位溝槽---> 5) 硅刻蝕---> 6) 進(jìn)一步硅刻蝕---> 7) 去除氧化物---> 8) 溝槽氧化---> 9) 多晶硅淀積---> 10) 多晶硅刻蝕---> 11) 氧化物刻蝕---> 12) 柵氧生長---> 13) 多晶硅淀積---> 14) 多晶硅刻蝕---> 15) P摻雜注入---> 16) 退火激活---> 17) N摻雜注入---> 18) 退火激活---> 19) 氧化物淀積---> 20) 光刻氧化層定位源接觸---> 21) 硅刻蝕---> 22) 源極金屬淀積

Sentaurus sprocess 工藝仿真代碼如下：

## ------------------------------------------------------------------------ ## Split-Gate VDMOS Device Process Simulation ## ------------------------------------------------------------------------mgoals accuracy= 1e-5 math coord.ucs pdbSet Grid SnMesh min.normal.size 0.005 pdbSet Grid SnMesh normal.growth.ratio.2d 1.5 pdbSet Grid SnMesh max.lateral.size 1.0refinebox interface.materials= SiliconpdbSet Grid Adaptive 1 pdbSet Grid Min.Adaptive.Temp 1200.0 refinebox name= Global adaptive Silicon \ refine.min.edge= "0.01 0.01" refine.max.edge= "1.0 1.0" \ abs.error= "Boron=1e15 Arsenic=5e16 Phosphorus=1e15" \ rel.error= "Boron=0.20 Arsenic=0.20 Phosphorus=0.20" \ max.dose.error= "Boron=1e10 Arsenic=1e10 Phosphorus=1e10"pdbSet Oxide Grid perp.add.dist 5.0e-7 pdbSet Silicon Grid Remove.Dist 2.0e-8 pdbSet Grid NativeLayerThickness 1.0e-7pdbSet Diffuse dThickness 6.0e-3AdvancedCalibrationmask name= m_trench segments= {0.8 1.2} negative mask name= m_contact segments= {0.0 0.3 1.7 2.0} negative## ------------------------------------------------------------- line x location= 0.0<um> spacing= 0.2<um> tag= top line x location= 1.0<um> spacing= 0.2<um> line x location= 4.0<um> spacing= 0.5<um> tag= bottomline y location= 0.0<um> spacing= 0.2<um> tag= left line y location= 2.0<um> spacing= 0.2<um> tag= rightregion Silicon xlo= top xhi= bottom ylo= left yhi= right substrate init Silicon field=Phosphorus concentration= 1e19 wafer.orient=100 !DelayFullDstruct tdr=1_initrefinebox name= ref_int min.normal.size= 0.1 normal.growth.ratio= 5.0 \interface.materials = { Silicon } min= { -1.0 0.0 } max= { 1.0 2.0 }## Epitaxy N-drift layer temp_ramp name= ramp_drift temperature= 550 t.final= 700 time=1<min> temp_ramp name= ramp_drift t.final= 700 time= 5<min> Epi thick= 6<um> \epi.doping = { phosphorus= 2e16 } diffuse temp.ramp= ramp_driftstruct tdr=2_epi### Oxide deposition of 100 nm thick deposit oxide thickness= 0.1 isotropicstruct tdr=3_oxide### trench etching ### etch oxide thickness=0.11 anisotropic mask= m_trenchstruct tdr=4_etch## Directional etching of Silicon to produce angled trenches etch time= 3 type= trapezoidal material= Silicon rate= 1.0 angle=89struct tdr=5_etchetch time= 1 type= isotropic material= Silicon rate= 0.1struct tdr=6_etchstrip oxide grid remeshstruct tdr=7_etch##-- Gate Oxidation temp_ramp name= GateOx time= 80 temperature= 700 t.final= 1100 temp_ramp name= GateOx time= 10 temperature= 1100 t.final= 1100 temp_ramp name= GateOx time= 40 temperature= 1100 t.final= 1100 pressure= 1 flowO2= 12 temp_ramp name= GateOx time= 10 temperature= 1100 t.final= 1100 temp_ramp name= GateOx time= 120 temperature= 1100 t.final= 700diffuse temp_ramp= GateOxstruct tdr=8_oxide## Polysilicon Deposition deposit polysilicon type=isotropic thickness=1.0 \ temperature=580 species= Phosphorus concentration= 1.0e19struct tdr=9_polyetch polysilicon type= cmp coord= -5.2struct tdr=10_etchetch oxide type= cmp coord= -5.2struct tdr=11_etch##-- Gate Oxidation temp_ramp name= GateOx1 time= 80 temperature= 700 t.final= 1100 temp_ramp name= GateOx1 time= 10 temperature= 1100 t.final= 1100 temp_ramp name= GateOx1 time= 15 temperature= 1100 t.final= 1100 pressure= 1 flowO2= 12 temp_ramp name= GateOx1 time= 10 temperature= 1100 t.final= 1100 temp_ramp name= GateOx1 time= 120 temperature= 1100 t.final= 700diffuse temp_ramp= GateOx1struct tdr=12_oxide## Polysilicon Deposition deposit polysilicon type=isotropic thickness=1.0 \ temperature=580 species= Phosphorus concentration= 1.0e19struct tdr=13_polyetch time= 10 type= isotropic material= polysilicon rate= 0.1struct tdr=14_etch## Pwell implant Boron dose= 1.0e13 energy= 80struct tdr=15_imptemp_ramp name= ramp_npwell time= 10.0<min> temp= 700.0<C> t.final= 850.0<C> temp_ramp name= ramp_npwell time= 1.0<min> temp= 850.0<C> t.final= 850.0<C> temp_ramp name= ramp_npwell time= 10.0<min> temp= 850.0<C> t.final= 700.0<C> diffuse temp_ramp= ramp_npwellstruct tdr=16_anneal## Nplus implant Arsenic dose= 4.0e15 energy= 80struct tdr=17_imptemp_ramp name= ramp_nplus time= 10.0<min> temp= 700.0<C> t.final= 850.0<C> temp_ramp name= ramp_nplus time= 1.0<min> temp= 850.0<C> t.final= 850.0<C> temp_ramp name= ramp_nplus time= 10.0<min> temp= 850.0<C> t.final= 700.0<C> diffuse temp_ramp= ramp_nplusstruct tdr=18_anneal## Oxide Deposition deposit oxide type=isotropic thickness=0.2struct tdr=19_oxideetch oxide thickness=0.3 anisotropic mask= m_contactstruct tdr=20_etchetch silicon thickness=0.2 anisotropicstruct tdr=21_etchdeposit Aluminum type=isotropic thickness=0.5struct tdr=22_metal## Contact definitions contact name= gate region= PolySilicon_2 !replace contact name= source region= PolySilicon_1 !replace contact name= source1 region= Aluminum_1 !replace contact name= drain box Silicon xlo= 3.9 xhi= 4.1 ylo= -0.1 yhi= 2.1struct smesh= 23_final

3、 電學(xué)特性

該分離柵VDMOS具有44.6V擊穿電壓，電勢分布及擊穿特性曲線如下：

其閾值電壓為4.5V，導(dǎo)通電流分布及轉(zhuǎn)移特性曲線如下：

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總結(jié)

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