狀態機-重疊序列檢測

題目描述
設計一個狀態機，用來檢測序列 1011，要求：

1、進行重疊檢測 即10110111 會被檢測通過2次

2、寄存器輸出，在序列檢測完成下一拍輸出檢測有效

注意rst為低電平復位

信號示意圖

畫出狀態轉移圖

`timescale 1ns/1nsmodule sequence_test2(input wire clk ,input wire rst ,input wire data ,output reg flag ); //*************code***********//parameter idle = 5'b00001;parameter state1 = 5'b00010;parameter state2 = 5'b00100;parameter state3 = 5'b01000;parameter state4 = 5'b10000;reg[4:0] c_state,n_state;always@(posedge clk or negedge rst)beginif(!rst)c_state <= idle;elsec_state <= n_state;endalways@(*)begincase(c_state)idle:beginif(data == 1'b1)n_state = state1;elsen_state = idle;endstate1:beginif(data == 1'b0)n_state = state2;elsen_state = state1;endstate2:beginif(data == 1'b1)n_state = state3;elsen_state = idle;endstate3:beginif(data == 1'b1)n_state = state4;elsen_state = state2;endstate4:beginif(data == 1'b1)n_state = state1;elsen_state = state2;enddefault:n_state = idle;endcaseendalways@(posedge clk or negedge rst)beginif(!rst)flag <= 1'b0;else if(c_state == state4)flag <= 1'b1;elseflag <= 1'b0;end //*************code***********// endmodule

方法二

`timescale 1ns/1nsmodule sequence_test2(input wire clk ,input wire rst ,input wire data ,output reg flag ); //*************code***********//parameter S0=0, S1=1, S2=2, S3=3, S4=4;reg [2:0] state, nstate;always@(posedge clk or negedge rst) beginif(~rst)state <= S0;elsestate <= nstate;endalways@(*) beginif(~rst)nstate <= S0;elsecase(state)S0 : nstate <= data? S1: S0;S1 : nstate <= data? S1: S2;S2 : nstate <= data? S3: S0;S3 : nstate <= data? S4: S2;S4 : nstate <= data? S1: S2;default: nstate <= S0;endcaseendalways@(posedge clk or negedge rst) beginif(~rst)flag <= 0;elseflag <= state==S4;end//*************code***********// endmodule 創作挑戰賽新人創作獎勵來咯，堅持創作打卡瓜分現金大獎

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